Changes between Version 4 and Version 5 of TBR/BSP/Eth_comm


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Timestamp:
Nov 10, 2018, 6:31:59 PM (11 months ago)
Author:
Kathryn
Comment:

Fixed table, superscript, and line break formatting on this page for GCI 2018

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  • TBR/BSP/Eth_comm

    v4 v5  
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    4 {{Infobox BSP
    5 |BSP_name     = Frasca ETHCOMM eth_comm
    6 |Manufacturer = Freescale Semiconductor
    7 |image        = [File:MPC860_IMAGE.jpg|{http://cache.freescale.com/files/graphic/product_motorola/MPC860_IMAGE.jpg}]
    8 |Board_URL    = http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC860
    9 |Architecture = Power Architecture™
    10 |CPU_model    = MPC8xx Core with 88 MIPS at 66 MHz (using Dhrystone 2.1); MPC860P - 106 MIPS at 80 MHz for the MPC860P 
    11 |Simulator    = Unspecified
    12 |Predecessor  = MC68360 QUICC
    13 |RAM          = 8Kb Dual Port RAM
    14 |NVMEM        = 4Kb Data Cache; MPC860P - 8Kb Data Cache
    15 |Serial       = Four SCCs (Serial Communication Controllers)
    16 Two SMCs (Serial Management Channels)
    17 One SPI (Serial Peripheral Interface)
    18 One I<sup>2</sup>C (Inter-Integrated Circuit) Port
    19 Parallel Interface Port
    20 |NICs         = Unspecified
    21 |Other        = Low Power Support
    22 Debug Interface
    23 3.3 V Operation with 5V TTL Compatibility
    24 32 Address Lines
    25 Complete Static Design (040 MHz Operation)
    26 Memory Controller (Eight Banks)
    27 }}
     4
     5||||   '''Infobox BSP'''   ||
     6||'''BSP_name'''     ||Frasca ETHCOMM eth_comm||
     7||'''Manufacturer''' ||Freescale Semiconductor||
     8||'''image'''        ||[[Image(http://cache.freescale.com/files/graphic/product_motorola/MPC860_IMAGE.jpg)]]||
     9||'''Board_URL'''    ||http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC860||
     10||'''Architecture''' ||Power Architecture™||
     11||'''CPU_model'''    ||MPC8xx Core with 88 MIPS at 66 MHz (using Dhrystone 2.1); MPC860P - 106 MIPS at 80 MHz for the MPC860P||
     12||'''Simulator'''    ||Unspecified||
     13||'''Predecessor'''  ||MC68360 QUICC||
     14||'''RAM'''          ||8Kb Dual Port RAM||
     15||'''NVMEM'''        ||4Kb Data Cache; MPC860P - 8Kb Data Cache||
     16||'''Serial'''       ||Four SCCs (Serial Communication Controllers)||
     17||                   ||Two SMCs (Serial Management Channels)||
     18||                   ||One SPI (Serial Peripheral Interface)||
     19||                   ||One I^2^C (Inter-Integrated Circuit) Port||
     20||                   ||Parallel Interface Port||
     21||'''NICs'''         ||Unspecified||
     22||'''Other'''        ||Low Power Support||
     23||                   ||Debug Interface||
     24||                   ||3.3 V Operation with 5V TTL Compatibility||
     25||                   ||32 Address Lines||
     26||                   ||Complete Static Design (040 MHz Operation)||
     27||                   ||Memory Controller (Eight Banks)||
     28
     29
    2830
    2931Freescale Semiconductor’s PowerQUICC™ MPC860 family is designed to deliver a versatile, on-chip integrated processor and
     
    3133= Overview =
    3234
    33 The MPC860 architecture integrates two processing blocks: the embedded 8xx core compatible with the Power Architecture™ technology instruction-set architecture (ISA), and the communications processor module (CPM). The CPM is a dedicated RISC-based communications engine designed to support four serial communications controllers (SCCs), providing a total of eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I<sup>2</sup>C interface. This dual-processor architecture is designed to provide superior performance over traditional architectures because the CPM offloads communications intensive processing from the embedded 8xx core. This partitioning frees up the 8xx core to perform other system functions.
     35The MPC860 architecture integrates two processing blocks: the embedded 8xx core compatible with the Power Architecture™ technology instruction-set architecture (ISA), and the communications processor module (CPM). The CPM is a dedicated RISC-based communications engine designed to support four serial communications controllers (SCCs), providing a total of eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I^2^C interface. This dual-processor architecture is designed to provide superior performance over traditional architectures because the CPM offloads communications intensive processing from the embedded 8xx core. This partitioning frees up the 8xx core to perform other system functions.
    3436= Key Features =
    3537
     
    4951 *   Embedded 8xx core designed to provide 106 MIPS (using Dhrystone 2.1) at 80 MHz
    5052Single-issue, 32-bit version of the embedded 8xx core with 32- x 32-bit fixed point registers
    51 <br />
     53[[BR]]
    52544 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available in 860P and 860DP)
    53 <br />
     55[[BR]]
    5456Memory management units with 32-entry TLBs and fully associative instruction and data TLBs
    5557
     
    5860 *    Communications processor module
    59618 KB dual-port RAM
    60 <br />
     62[[BR]]
    6163Up to four serial communications controllers (SCCs)
    62 <br />
     64[[BR]]
    636532-bit scaler RISC controller
    64 <br />
     66[[BR]]
    6567Two serial management controllers
    66 <br />
     68[[BR]]
    676916 serial DMA (SDMA) channels
    68 <br />
     70[[BR]]
    6971One I2C port
    70 <br />
     72[[BR]]
    7173One serial peripheral interface
    72 <br />
     74[[BR]]
    7375Four general-purpose timers
    74 <br />
     76[[BR]]
    7577Time slot assigner
    76 <br />
     78[[BR]]
    7779Interrupts
    78 <br />
     80[[BR]]
    7981Four baud rate generators
    80 <br />
     82[[BR]]
    8183Protocols supported
    8284#Ethernet IEEE®802.3 and Fast Ethernet
     
    9496 *    System integration unit
    9597Memory controller
    96 <br />
     98[[BR]]
    9799Real-time clock
    98 <br />
     100[[BR]]
    99101PCMCIA interface
    100 <br />
     102[[BR]]
    101103System functions
    102 <br />
     104[[BR]]
    103105Bus interface unit
    104106