Changes between Version 1 and Version 2 of TBR/BSP/Eth_comm


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Timestamp:
Jan 6, 2013, 8:11:53 PM (7 years ago)
Author:
SudhaGranger
Comment:

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  • TBR/BSP/Eth_comm

    v1 v2  
    11= Eth comm =
     2
     3
     4{{Infobox BSP
     5|BSP_name     = Frasca ETHCOMM eth_comm
     6|Manufacturer = Freescale Semiconductor
     7|image        = [wiki:File:MPC860_IMAGE.jpg File:MPC860 IMAGE.jpg]
     8|Board_URL    = http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC860
     9|Architecture = Power Architecture™
     10|CPU_model    = MPC8xx Core with 88 MIPS at 66 MHz (using Dhrystone 2.1); MPC860P - 106 MIPS at 80 MHz for the MPC860P 
     11|Simulator    = Unspecified
     12|Predecessor  = MC68360 QUICC
     13|RAM          = 8Kb Dual Port RAM
     14|NVMEM        = 4Kb Data Cache; MPC860P - 8Kb Data Cache
     15|Serial       = Four SCCs (Serial Communication Controllers)
     16Two SMCs (Serial Management Channels)
     17One SPI (Serial Peripheral Interface)
     18One I<sup>2</sup>C (Inter-Integrated Circuit) Port
     19Parallel Interface Port
     20|NICs         = Unspecified
     21|Other        = Low Power Support
     22Debug Interface
     233.3 V Operation with 5V TTL Compatibility
     2432 Address Lines
     25Complete Static Design (040 MHz Operation)
     26Memory Controller (Eight Banks)
     27}}
     28
     29Freescale Semiconductor’s PowerQUICC™ MPC860 family is designed to deliver a versatile, on-chip integrated processor and
     30peripheral combination that can be used in a variety of controller applications—excelling particularly in communications and networking products. Providing functionality beyond the MPC850 family, the MPC860 family and MPC855T derivative are engineered to provide higher performance in all areas of device operation including flexibility, extensions in capability and integration.
     31= Overview =
     32
     33The MPC860 architecture integrates two processing blocks: the embedded 8xx core compatible with the Power Architecture™ technology instruction-set architecture (ISA), and the communications processor module (CPM). The CPM is a dedicated RISC-based communications engine designed to support four serial communications controllers (SCCs), providing a total of eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I<sup>2</sup>C interface. This dual-processor architecture is designed to provide superior performance over traditional architectures because the CPM offloads communications intensive processing from the embedded 8xx core. This partitioning frees up the 8xx core to perform other system functions.
     34= Key Features =
     35
     36 *  Power Architecture Technology Embedded 8xx core
     37 *   4 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available) in MPC860P and MPC860DP
     38 *   Powerful memory controller and system functions
     39 *   Efficient architecture that involves a separate RISC processor (CPM) for handling communications
     40 *   Up to four serial communications controllers (SCC)
     41 *   Support for Ethernet, Fast Ethernet, HDLC, asynchronous transfer mode (ATM) and more
     42 *   Two SMCs, one SPI and one I<sup>2</sup>C
     43 *   Additional support features, including timers, baud rate generators, etc.
     44 *   8K dual-port RAM
     45 *  Available at 50, 66 and 80 MHz in a 357-pin RoHS compliant PBGA package
     46 *   Strong third-party tool support through Freescale’s Design Alliance Program
     47 *   Embedded 8xx core designed to provide 106 MIPS (using Dhrystone 2.1) at 80 MHz
     48Single-issue, 32-bit version of the embedded 8xx core with 32- x 32-bit fixed point registers
     49<br />
     504 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available in 860P and 860DP)
     51<br />
     52Memory management units with 32-entry TLBs and fully associative instruction and data TLBs
     53
     54 *   Advanced on-chip emulation debug mode
     55 *  Data bus dynamic bus sizing for 8-, 16- and 32-bit buses
     56 *    Communications processor module
     578 KB dual-port RAM
     58<br />
     59Up to four serial communications controllers (SCCs)
     60<br />
     6132-bit scaler RISC controller
     62<br />
     63Two serial management controllers
     64<br />
     6516 serial DMA (SDMA) channels
     66<br />
     67One I2C port
     68<br />
     69One serial peripheral interface
     70<br />
     71Four general-purpose timers
     72<br />
     73Time slot assigner
     74<br />
     75Interrupts
     76<br />
     77Four baud rate generators
     78<br />
     79Protocols supported
     80#Ethernet IEEE®802.3 and Fast Ethernet
     81#ATM
     82# HDLC
     83#Asynchronous HDLC
     84#Channelized HDLC
     85#Multi-channel HDLC
     86#Appletalk®
     87# UART
     88# IrDA
     89# Basic rate ISDN (BRI)
     90#Primary rate ISDN (PRI)
     91# Totally transparent mode with/ without CRC
     92 *    System integration unit
     93Memory controller
     94<br />
     95Real-time clock
     96<br />
     97PCMCIA interface
     98<br />
     99System functions
     100<br />
     101Bus interface unit
     102
    2103
    3104=  References  =