wiki:TBR/BSP/Eth_comm

Eth comm

{{Infobox BSP |BSP_name = Frasca ETHCOMM eth_comm |Manufacturer = Freescale Semiconductor |image = [File:MPC860_IMAGE.jpg|{http://cache.freescale.com/files/graphic/product_motorola/MPC860_IMAGE.jpg}] |Board_URL = http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC860 |Architecture = Power Architecture™ |CPU_model = MPC8xx Core with 88 MIPS at 66 MHz (using Dhrystone 2.1); MPC860P - 106 MIPS at 80 MHz for the MPC860P |Simulator = Unspecified |Predecessor = MC68360 QUICC |RAM = 8Kb Dual Port RAM |NVMEM = 4Kb Data Cache; MPC860P - 8Kb Data Cache |Serial = Four SCCs (Serial Communication Controllers) Two SMCs (Serial Management Channels) One SPI (Serial Peripheral Interface) One I<sup>2</sup>C (Inter-Integrated Circuit) Port Parallel Interface Port |NICs = Unspecified |Other = Low Power Support Debug Interface 3.3 V Operation with 5V TTL Compatibility 32 Address Lines Complete Static Design (040 MHz Operation) Memory Controller (Eight Banks) }}

Freescale Semiconductor’s PowerQUICC™ MPC860 family is designed to deliver a versatile, on-chip integrated processor and peripheral combination that can be used in a variety of controller applications—excelling particularly in communications and networking products. Providing functionality beyond the MPC850 family, the MPC860 family and MPC855T derivative are engineered to provide higher performance in all areas of device operation including flexibility, extensions in capability and integration.

Overview

The MPC860 architecture integrates two processing blocks: the embedded 8xx core compatible with the Power Architecture™ technology instruction-set architecture (ISA), and the communications processor module (CPM). The CPM is a dedicated RISC-based communications engine designed to support four serial communications controllers (SCCs), providing a total of eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI) and one I<sup>2</sup>C interface. This dual-processor architecture is designed to provide superior performance over traditional architectures because the CPM offloads communications intensive processing from the embedded 8xx core. This partitioning frees up the 8xx core to perform other system functions.

Key Features

  • Power Architecture Technology Embedded 8xx core
  • 4 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available) in MPC860P and MPC860DP
  • Powerful memory controller and system functions
  • Efficient architecture that involves a separate RISC processor (CPM) for handling communications
  • Up to four serial communications controllers (SCC)
  • Support for Ethernet, Fast Ethernet, HDLC, asynchronous transfer mode (ATM) and more
  • Two SMCs, one SPI and one I<sup>2</sup>C
  • Additional support features, including timers, baud rate generators, etc.
  • 8K dual-port RAM
  • Available at 50, 66 and 80 MHz in a 357-pin RoHS compliant PBGA package
  • Strong third-party tool support through Freescale’s Design Alliance Program

Technical Specifications

  • Embedded 8xx core designed to provide 106 MIPS (using Dhrystone 2.1) at 80 MHz

Single-issue, 32-bit version of the embedded 8xx core with 32- x 32-bit fixed point registers <br /> 4 KB instruction cache and 4 KB data cache (16 KB instruction cache and 8 KB data cache available in 860P and 860DP) <br /> Memory management units with 32-entry TLBs and fully associative instruction and data TLBs

  • Advanced on-chip emulation debug mode
  • Data bus dynamic bus sizing for 8-, 16- and 32-bit buses
  • Communications processor module

8 KB dual-port RAM <br /> Up to four serial communications controllers (SCCs) <br /> 32-bit scaler RISC controller <br /> Two serial management controllers <br /> 16 serial DMA (SDMA) channels <br /> One I2C port <br /> One serial peripheral interface <br /> Four general-purpose timers <br /> Time slot assigner <br /> Interrupts <br /> Four baud rate generators <br /> Protocols supported #Ethernet IEEE®802.3 and Fast Ethernet #ATM # HDLC #Asynchronous HDLC #Channelized HDLC #Multi-channel HDLC #Appletalk® # UART # IrDA # Basic rate ISDN (BRI) #Primary rate ISDN (PRI) # Totally transparent mode with/ without CRC

  • System integration unit

Memory controller <br /> Real-time clock <br /> PCMCIA interface <br /> System functions <br /> Bus interface unit

References

# http://en.wikipedia.org/wiki/PowerQUICC # http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=MPC860 # http://opencores.org/ocsvn/openrisc/openrisc/trunk/rtos/rtems/make/custom/eth_comm.cfg

Last modified on Jan 6, 2013 at 8:21:17 PM Last modified on Jan 6, 2013, 8:21:17 PM