Changes between Version 4 and Version 5 of TBR/BSP/Erc32


Ignore:
Timestamp:
Jan 4, 2013, 9:45:58 PM (7 years ago)
Author:
C Rempel
Comment:

Contributed by Ayush as part of Google Code In 2012

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  • TBR/BSP/Erc32

    v4 v5  
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     4{{Infobox BSP
     5
     6| BSP_name  = Tharsy
     7| Manufacturer = TEMIC (now ATMEL)
     8| Reference       = http://www.atmel.com/Images/doc7503.pdf
     9| Architecture  = SPARC V7
     10| CPU Model    = ERC32
     11| Runs on Simulator = SPARC Instruction  GDB Simulator
     12| RAM               = 256K - 32M
     13| Serial Ports = Serial Ports Unspecified
     14}}
    415This BSP is for the space hardened SPARC V7 processor developed by the European Space Agency and in use by numerous projects.  The ERC32 includes serial ports and timers on the CPU so one BSP can support many of the ERC32 boards.
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