wiki:TBR/BSP/Erc32

Erc32

{{Infobox BSP

| BSP_name = Tharsy | Manufacturer = TEMIC (now ATMEL) | Board_URL = http://www.atmel.com/Images/doc7503.pdf | Architecture = SPARC V7 | CPU_model = ERC32 | Simulator = SPARC Instruction GDB Simulator | RAM = 256K - 32M | Serial = Serial Ports Unspecified }} This BSP is for the space hardened SPARC V7 processor developed by the European Space Agency and in use by numerous projects. The ERC32 includes serial ports and timers on the CPU so one BSP can support many of the ERC32 boards.

There is a Tharsys board which includes a network interface. This BSP can be configured to support that board as well.

The startup procedure for the Erc32 and Leon BSPs is explained in SparcBSPStartup.

NOTE: As of October 2005, one must use the sis BSP variant to run this BSP on the SPARC Instruction Simulator included in GDB. There are differences between the behavior of this simulator and the real hardware which require extra initialization code.

Test Reports

4.6.4: User:JoelSherrill? reports that it runs fine on the SIS in gdb 5.3.

4.6.99.2: User::JoelSherrill? reports that it runs fine on the SIS in gdb 6.3 once you disable the code section in start.s which copies initialized data from ROM to RAM.

4.7-branch 2006-11-15: [[User:JoelSherrill]] reports that all tests except psx06 run using tsim-erc32.

Last modified on Jan 4, 2013 at 9:50:17 PM Last modified on Jan 4, 2013, 9:50:17 PM