wiki:TBR/BSP/Dmv152

Dmv152

{{Infobox BSP |BSP_name = DY-4 DMV152 |Manufacturer = Dy 4 Systems |image = DY4 dmv152.jpg |caption = DMV152 |Board_URL = http://www.artisan-scientific.com/info/DY4_SVME_153_Datasheet.pdf |Architecture = M68K |CPU_model = 20 MHz 68020 CPU, optional '882 FPP |Monitor = DyBug? |Simulator = N/A |Aliases = DMV152 |RAM = 4M Bytes of SRAM |NVMEM = Flash EPROM (1.5M Bytes), EEPROM(3M Bytes), EPROM(6M Bytes) |Serial = 2 Serial Channels are provided by 8530 Serial Communication Controller |Video = Video Unspecified }}= Overview =

<h4>Features</h4>

  • 20 MHz 68020 CPU, optional '882 FPP
  • Ten 32-pin JEDEC sites for: *Four sites for SRAM *Four sites for SRAM, EPROM, Flash™ EPROM, or EEPROM *Two sites for EPROM, Flash™ EPROM, or EEPROM (boot) *SRAM capacity up to 4M bytes
  • 512 byte serial EEPROM
  • Card-edge boot EPROM programmability
  • Two serial channels, software-selectable EIA-232-C or EIA-485/422 compatible
  • Three 16-bit timers
  • Three P2 I/O lines
  • Advanced VMEbus Interface Chip Set (AVICS) *A32:D32 VMEbus interface *Transmit and Receive FIFOs *DMA driven VMEbus transfers *Location monitor with FIFO buffer *System Controller functions *Auto-ID and Auto-SYSCON *Two P2 interrupt inputs
  • Built-In-Test (BIT)
  • Bus Isolation mode (BI-mode®)
  • Conduction cooled per IEEE 1101.2 (0.65-inch pitch) for MIL-E-5400/4158, and MIL-STD-2036 applications
  • Optional levels of ruggedization available

Board Setup

<h4>Dmv-152</h4>

The card supports DY 4 Systems' common features including an AVICS-based VMEbus interface, Built-In-Test (BIT), BI-mode, location monitor, and Auto ID. These features bring benefits in performance, logistics and maintenance. DY 4's custom-designed AVICS chip-set implements all VMEbus interface functions with software-programmable features. It combines low-latency access to the VMEbus with high sustained throughputs. Built-In-Test (BIT) hardware features verify all operational circuits on the module. Bus Isolation mode (BI-mode®) increases ease of testing and system fault location. The location monitor supports efficient interprocessor messaging, to minimize overhead in real-time software. Auto-ID allows boards to be self-configuring, based on slot location. These features allow users to:

  • build high-performance multi-processor systems
  • detect and isolate faults during operation
  • minimize field maintenance and sparing logistics.

All versions of the SVME-153/DMV-152 are functionally identical. SVME versions for use in air-cooled environments are available in DY 4 ruggedization levels 0, 2 and 3. The conduction-cooled DMV version is designed for airborne, land-mobile, and naval military applications where circuit cards are sealed in a chassis to prevent moisture, salt- fog, sand, and dust contamination. DY 4 Systems' conduction-cooled products are designed for severe environmental conditions defined by MIL-E-4158, MIL-E-5400, and MIL- STD-2036. A single-piece aluminum thermal plane bonded to the PWB conducts heat away from the electronics. Its integral stiffening ribs improve heat dissipation and vibration resistance. Standard wedgelock fasteners give a reliable thermal connection to the chassis.

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<h4>Memory</h4>

The SVME-153/DMV-152 uses ten 32-pin JEDEC sites for all memory. It supports the following configurations. There are three banks of memory; two banks have four 32-pin JEDEC sites and the third bank has only two 32-pin JEDEC sites. Bank 0 is installed with SRAM devices, Bank 1 can be populated with SRAM, Flash™ EPROM, EEPROM, or EPROM devices, and the third bank (the Boot PROM), can be installed with Flash™ EPROM, EEPROM, or EPROM devices. To facilitate the use of the SVME-153/DMV- 152 in severe vibration environments where all components must be soldered, the EPROM in Bank 3 (Boot EPROM) may be programmed on-board (by placing the card in a programming fixture). This simplifies the installation of application code and makes on- site firmware upgrades possible. Refer to the CCA-830 On-Board Programming Adapter, document number MS00154. The SVME-153/DMV-152 also has 512 bytes of EEPROM for storing configuration data.

<h4>VMEbus Interface</h4>

A complete VME master interface is capable of A32, A24, and A16 addressing modes and D32, D16, and D08 (EO) data transfers. A VME interrupt handler is also provided. The VMEbus is supported by DY 4's Advanced VMEbus Interface Chip Set (AVICS). This chip set consists of the ACC (ASA (Advanced System Architecture) Control Circuit) and the DARF (Data Address Register File). The ACC device places all system controller and interrupt functions for the VMEbus in a single package. This custom ASIC allows full programmability of requester modes and levels, arbiter modes, bus timers, interrupt grouping, and acknowledge techniques. The ACC also provides extensive BIT features and BI-mode®. The DARF provides a fast efficient means of supporting the design limit of a 40M byte per second bus transfer rate. This is a result of a decoupled FIFO buffering mechanism between the local and VME buses. High- speed transfers are effectively transparent to the software and in full compliance to the IEEE 1014 bus specifications. The design allows for complete VMEbus data integrity through extensive BIT and BI-mode features.

<h4>Serial Channels</h4>

Two serial channels are provided by a 8530 Serial Communication Controller. Each channel is capable of supporting EIA-232-C or EIA-485/422 modes of operation. The mode of operation is software-selectable. In EIA-485/422 serial mode, the following signals on the Serial Communications Controller (SCC) are used:

  • TxD and RxD
  • TRxC and RTxC (strapping option)
  • CTS and RTS (strapping option only on

JEDEC site version). In EIA-232-C serial mode, TxD, RxD, RTS, and CTS are used. The software-selectable serial mode affects the selection of receivers used, (EIA-232-C or EIA-485/422). The serial channels are driven with a 2.4615 MHz clock and provide asynchronous communications with baud rates from 50 baud to 19.2K baud, and synchronous communications at rates up to 600K bits/sec.

<h4>Timer</h4>

The SVME-153/DMV-152 incorporates a 8536 Counter/Timer? and I/O device (CIO). This device provides three 16-bit timers; all timers can be used as general purpose timers with vectored interrupt capability. An on-board tick timer can be programmed to interrupt the CPU at regular intervals. A watchdog timer provides a fail indication and resets the CPU if it detects an execution failure.

Downloading and Executing

Describe the download procedure.

Debugging

The SVME-153/DMV-152 is supplied with a foundation firmware package which includes a General Purpose Monitor (GPM), providing comprehensive monitoring and debug functions for the system integrator.

Test Reports

{{Test Report |Version = CVS head |Date = DATE |User = User:WhoTestedThis? }}

References

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Last modified on Jan 7, 2013 at 9:43:00 PM Last modified on Jan 7, 2013, 9:43:00 PM