- Timestamp:
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05/25/15 12:45:06 (9 years ago)
- Author:
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Hesham Almatary
- Comment:
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Add generic_or1k and epiphany_sim BSPs
Legend:
- Unmodified
- Added
- Removed
- Modified
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v12
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v13
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123 | 123 | |
124 | 124 | * Added support for the [http://moxielogic.org/wiki/index.php/Main_Page Moxie] open source processor architecture. |
125 | | * Added support for the [http://opencores.org/or1k/Main_Page OpenRISC] open source processor architecture (target=or1k). |
| 125 | * Added support for the [http://opencores.org/or1k/Main_Page OpenRISC (or1k)] open source processor architecture (target=or1k). |
126 | 126 | * Added support for the [http://adapteva.com/docs/epiphany_arch_ref.pdf Epiphany] processor (eCore) architecture (target=epiphany). |
127 | 127 | * Added support for the SPARC V9 CPU family, a 64-bit processor architecture (target=sparc64). |
… |
… |
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152 | 152 | * BSPs for bfin |
153 | 153 | * [wiki:TBR/BSP/TLL6527M TLL6527M] |
| 154 | * BSPs for Epiphany |
| 155 | * epiphany_sim - It runs on the Epiphany default simulator. |
154 | 156 | * BSPs for moxie |
155 | 157 | * moxiesim |
| 158 | * BSPs for OpenRISC (or1k) |
| 159 | * generic_or1k - This BSP can run on or1ksim (the main or1k simulator), QEMU, jor1k and a real or1k supported FPGA board (has been tested on Atlys board). |
156 | 160 | * BSPs for sparc64 cpu model |
157 | 161 | * [wiki:Niagara_ niagara: UltraSPARC T1] |