MMU Support

Student : Aanjhan Ranganathan, Quanming Shi, Hesham Al-Matary

Mentor : Thomas Doerfler, Peter Dufault, Gedare Bloom


Most modern processors have memory management unit (MMU) or memory protection unit (MPU) hardware whose main functions are virtual address translation, memory protection, and cache control. With RTEMS primarily focused on Real-Time/Embedded? applications, making use of these MMU features is important to meet the needs of applications and platforms that require such support. RTEMS currently does not have general MMU support, and this project seeks to add general MMU capabilities within RTEMS.

  • XXX comment on use of MMU versus full process model *= Design Notes =


Low Level APIs

Low level APIs will be used to perform operations such as initialisation of MMU registers, PTE generation and storage, exception handling. Except for Exception Handling APIs which shall be triggered from the MMU H/w, the rest will be called by the BSP functions.

Since most of the above actions are architecture specific these APIs shall belong to the libCPU section of RTEMS. Placing it in score/cpu is also an option but since there are varied MMU architectures for the same CPU, it would be better of to place it in libCPU.

The interaction between the different levels of the API is shown in the below sequence diagram.

No image "sequence_diagram.png" attached to Projects/MMU_Support

Mid Level APIs

The middle layer of the implementation would be architecture independent. This would not just be APIs but is also the layer where the functionality of several actions are going to be present. The complete implementation can fit into the cpukit layer of RTEMS software architecture.

One major functionality of this mid-layer is to manage the 'OS maintained Memory blocks' and assign access attributes. These memory blocks shall be grouped by "contexts". For. E.g each task creates a "MMU Context" which points to a data structure (to be defined) of memory blocks. Each memory block then has attributes associated like "read-only", "don't execute" , "cache-inhibit", "cache-write-through" etc. There shall be APIs to generate/modify/remove these memory blocks which can be used by the higher level applications.

Also there shall be another set of APIs which shall be used by the low level BSP functions to extract information with respect to access rights for a particular block, the access attributes to use etc. This information will then be used by the Low level software to update/create the PTE. Also, a mechanism to inform the low level system of any invalidation/removal/change of status of a memory block is needed. This ensures that the PTE are kept upto date in case of removal of any memory areas.

Once the data structure for these memory blocks are in place, then there shall exist APIs to create/modify/add entries into the memory block database.

Note : Need to find a better name for these memory block database.

The Work package Flow

This section shall describe the work package in steps that makes it easy to comprehend and evaluate ones progress. Also this enables us to have fixed goals at various stages of the project.

The various steps can be broadly classified as below

# An API/MMU Port Design Document # Software Architecture decisions (Part of 1 in a way) # Operating Support for Initialisation of MMU - Implementation # Page Table Entry generation (hash tables, exception handling) # Adding a PTE # Removing PTE # POSIX API and

API/MMU Port Design Document

This will be Part 1 and 2 of the package. The document shall describe the various functions planned to support in the Package, Initialisation sequence, Exception handling. Also would contain a brief Software Architecture description (E.g. what shall go into the SuperCore?, what shall go into the libchip etc. A kind of a functional flow diagram)

OS Support for MMU Initialisation

The next step in the package would be to get the initialisation of the MMU registers in place. This cannot be tested as such except through reviews since no access to the MMU will be allowed until a PTE is defined.

Page Table Entry Handling

Defining a Page Table entry is implemented here. This would be according to the information available beginning from Section 7.6.2 of the Programmer's Manual for PPC doc [2]. After defining the page entry, the next step is to put this info into the MMu table.

In other words, the next phases would involve implementing

  • Adding the PTE
  • Removing the PTE from the table.

A deeper look into the generation and storing of the PTEs would lead to one realising that there is not enough space in each PTEG (or hash table) and not all translation info can go into this hardware buffer. Hence there is a necessity to maintain a separate data structure containing info useful for generating the PTE.

For. e.g. let's say the PPC core tries to access an address that is not stored in the data TLB of the MMU H/W. Then the PPC will issue a "Data TLB miss exception". The data TLB miss exception will use some magic registers to access the PPTEG - the primary page table entry group. It will search this group for a PTE with a proper pattern. There are about 8 entries in a PPTEG, hence it is possible that the entry is not fond in the primary group and hence the search moves on to the SPTEG. Though the probability of finding the required pattern in SPTEG is more than in the PPTEG, still there is no guarantee. If found, the entry is put into the TLB and function returns. If it fails then the exception rised by the MMU should lead to a look up into a "OS maintained memory table" to create the required PTE and store it in the hash table/insert into the TLB.

This exception handling function needs to be implemented as part of the package too.

POSIX based Memory Protection

Suitability of a POSIX API implementation needs to be explored. All the above implementation are at a lower level in the software design tree and the POSIX APIs work at much higher level. But to come to a concrete decision more study is required. The shmem API is a good starting point.

This makes the work package until now.


{| | PTE | Page Table Entry

| PPTEG | Primary Page Table Entry Group

| SPTEG | Secondary Page Table Entry Group

| VSID | Virtual Segment Identifier

| API | Abbreviated Page Index

| TLB | Translation lookup Buffer

| EA | Effective Address |}


[1] ?Minix PPC document

[2] Programmers manual of PPC

Last modified on Feb 16, 2013 at 1:27:10 AM Last modified on Feb 16, 2013, 1:27:10 AM

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