wiki:Projects/GSoC/OpenRISC

OpenRISC Port

Mentors: Ben Gras, Chris Johns, Christian Svensson

Students: Hesham ALMatary

Status: The basic porting process is complete. All the code is merged. There is now generic_or1k BSP for or1k CPU architecture that can run almost all of the tests. generic_or1k BSP can run on QEMU, or1ksim, jor1k and real FPGA boards.

Introduction: The project aims to port RTEMS to OpenRISC architecture.

Goal: The overall goal of the project is to have a long-term reliable port of RTEMS to OpenRISC. This requires working on three different sub-tasks: tool-chain, RTEMS cpukit, and BSP(s).

  • tool-chain: Basic tools needed to compile and build RTEMS for or1k.
  • RTEMS/cpukit: Common OpenRISC architecture code that all or1k targets share.
  • BSP(s): The front-end interface for OpenRISC architecture including drivers like: UART, Timer, and/or IRQ.

File:OpenRISC Port Project.jpg?

tool-chain?

Currently, or1k folks are working on submitting their tool-chain upstream, binutils has already been merged. When this project reaches a stable state, the code for building the tool-chain for RTEMS should be upstream too (after or1k code has been merged). Meanwhile, all the work in this area is some sort of patches that can referenced from RSB.

  • binutils: By now, binutils support for or1k architecture is now upstreamed to cvs.
  • newlib: setjmp/longjmp have been provided along with all other necessary configurations and/or code to build gcc/newlib for RTEMS. newlib work is now upstreamed to cvs without any libgloss stuff. There is a newly added patch for newlib/or1k which has not been tested yet.
  • GCC: It's now building with newlib and able to compile all RTEMS code for or1k targets. We and OpenRISC folks are working to push the code soon to GCC upstream.
  • GDB: For GDB, it's now able to debug any or1k/RTEMS code by connecting it remotely to or1ksim emulator.
  • or1ksim: It's able to run test cases and used for debugging purposes along with GDB. There is a configuration script that must be provided though that describes the architecture specifications and supported devices (exists in the generic_or1k BSP directory).

RTEMS?

A new cpukit/cpu/or1k directory has been added to support the new OpenRISC port. This includes basic functions which are necessary for RTEMS to run any OpenRISC programs. The following are some of these functions:

  • Context Switch: It's needed for any OS that requires multi-tasking operations. Simply, it's a similar version of setjmp/longjmp written in assembly. Since context switch is more like function calls, only callee-destroyed registers are stored (and other interrupt context registers).
  • ISR_Handler: a generic ISR handler is provided which contains prologue code that handles isr_level, disabling interrupts, disabling multi-tasking, store interrupted task context, and then jump to the C handler from a vector table. After ISR C routine returns back, the context is restored, and a check for dispatch_needed is done to decide whether a context switch is necessary or not and if so do the magic and jump to _Thread_Dispatch.

Currently there are only two levels of interrupts: disable/enable. In the future, fast context switch support could be added which supports up to 15 levels. Also ISR disable/enable routines are provided there.

  • CPU initialization: This routine simply set stack and frame pointers along with setting return address to the entry point of the program.
  • CPU architecture configurations: OR1K port provide the architecture specifications at cpukit. Some important configurations like: in which direction the stack grows (down for or1k), how interrupt stack is allocated, other features existence like FP support. Also context control, interrupt control structures are provided there. Most of these configurations can be found at or1k/cpu.h
  • print context control: this is a helper routine that prints out the context control information in a readable way just for debugging purposes.

BSP(s)?

= generic_or1k =

generic_or1k (previously ork1sim) is a new BSP that can run on QEMU, or1ksim, jor1k and real FPGA boards. It's the first implemented interface for OpenRISC targets. It provides the following functions:

  • Start code: the necessary start code for the BSP which contains the vector table slots, HW exceptions addresses, start code which set up the stack, clear .bss and jump to bootcard.
  • Clock driver: The generic_or1k BSP provides a clock driver with an external clock of 50 MHz necessary for task scheduling and multi-tasking.
  • UART driver: It simply provides the low-level implementation for initialization, putc, and uart write functions needed to be able to emit some output to stdout.

TODO?

  • MMU handling.
  • Cache handling.
  • Timer benchmark.
  • Fast context switch code.
  • TLS support.
  • FP support.

Requirements: Developers who wish to contribute to this project should have a fair knowledge with C programming, OpenRISC architecture, and/or GNU tool-chain internals.

Howto TBD

Tasks TBD

Resources:

[1] or1k page at opencores.org

[2] or1k repositories at github

[3] Hesham ALMatary repositories at github

Acknowledgements TBD

Miscellaneous Sections

Acronyms

or1k: OpenRISC 1000 architecture.

RSB: RTEMS Source Builder.

=References=

  • TBD
Last modified on Apr 19, 2015 at 11:26:53 AM Last modified on Apr 19, 2015, 11:26:53 AM