Memory Protection

Ticket: ​https://devel.rtems.org/ticket/2904

Mentors: Peter Dufault, Hesham, Gedare, Sebastian Huber

Student: Utkarsh Rai

Blog: ​https://gsoc2020memoryprotection.blogspot.com/

Introduction

Most modern processors have a memory management unit (MMU) or memory protection unit (MPU) hardware whose main functions are virtual address translation, memory protection, and cache control. RTEMS primarily focuses on Real-Time/Embedded? applications, making use of these MMU features is important to meet the needs of applications and platforms that require such security-critical support. RTEMS currently does not have robust protection for thread stacks. Thread stack protection is one of the more interesting features that can be implemented using MMU. This will allow users to explicitly define the thread stacks they want to access from another thread and will raise an exception in any other case.

For more information, please refer to the proposal: ​https://docs.google.com/document/d/1AawmqbfCpRDHZ4cO5-UE1J7VacubNWmn3kae4rlPrZA/edit?usp=sharing

Phase 1 Goals

• To provide lower level dynamic page table loading support for ARMv7-A based processors (Work to be carried out on xilinx_zynq_a9_qemu BSP)
• Attribute translation support for different memory access permission for supporting all architectures
• Low level architecture specifc mechanism to share the thread stacks for AMV7-A processors
• Higher level POSIX support for sharing thread stacks.