Changes between Version 2 and Version 3 of GSoC/2017/RTEMS_for_HiFive1


Ignore:
Timestamp:
08/15/17 23:56:53 (7 years ago)
Author:
Denis Obrezkov
Comment:

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  • GSoC/2017/RTEMS_for_HiFive1

    v2 v3  
    1212
    1313'''Project Objectives''': At the of the project I want to have a working with capabilities of task switching and interrupt handling. Another objective is haveing working console and clock drivers.
     14
     15== Board Overview ==
     16
     17= Tms570 =
     18
     19||BSP Information
     20||BSP_name     || HiFive1 (FE310-G000)
     21||Manufacturer || SiFive
     22||Board_URL    || https://www.sifive.com/documentation/boards/hifive1/hifive1-overview/
     23||Architecture || RISC-V
     24||Piveleged ISA|| 1.9
     25||CPU_model    || SiFive Freedom E310 (FE310)
     26||Simulator    || Yes (spike)
     27||RAM          || 16 KB Instruction Cache, 16 KB Data Scratchpad
     28||ROM          || 16 MB SPI Flash
     29||Serial       || 2 x UARTs (1 available), 2 x SPI (+1 Flash)
     30||Dimensions   || 68 mm x 51 mm
     31||Other        || 19 Digital I/O pins
    1432
    1533== Description and references ==