Changes between Version 163 and Version 164 of GSoC/2015


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Timestamp:
Jun 23, 2015, 4:53:25 PM (4 years ago)
Author:
Jarielle Catbagan
Comment:

Added status update for June 23, 2015

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  • GSoC/2015

    v163 v164  
    156156* June 16: Since the last status update, I elaborated extensively the approach that I am taking in porting Umon as well as the fundamentals of DDR3 SDRAMs which can be found in my blog.  I have also consolidated all the necessary information that pertain to the composition, operation, and requirements of DDR3 and I am currently implementing the DDR3 configuration in rom_reset.S.  The BBB that I have has a 512MB DDR3 SDRAM, which is the D2516EC4BXGGB from Kingston, and I have already familiarized myself with the parameters of the DDR3 as it is required during the DDR3 configuration.  The memory subsystem on the AM335x, and subsequently on the BBB, that interfaces with the DDR3 SDRAM is the EMIF subsystem as specified in section 7.3 in the AM335x TRM.  Fortunately, TI has a dedicated wiki that provides tips and insights on the configuration of these registers within the EMIF subsystem in order to interface with DDR3.  There is also essential information in the JEDEC DDR3 Standard specification, in particular section 3.3.1, as it concisely summaries the sequence of steps required in order to reset and initialize DDR3 properly.  As a result, this is also utilized as reference for the current DDR3 implementation effort.  There are also the DDR PHY registers that must be configured accordingly based on the characteristics of the board where the DDR3 exists in order to ensure that proper timing is performed for all DDR transactions.  Additionally, the clocks going into the DDR memory must also be configured as specified in section 7.3.3.2 in the AM335x TRM.  The information that will be utilized to configure the DDR clocks is in section 8.1.6.11 in the AM335x TRM as well.  Once the DDR3 configuration is implemented, a simple test that I will be performing to ensure that the DDR3 is setup properly is by manipulating predetermined values within the DDR3 memory range and then outputting the values through UART0.  This memory range of the EMIF subsystem, and as a result it is also the memory that can be allocated to DDR3, is 0x80000000 - 0xBFFFFFFF.  This is equivalent to 1GB.  The modifications/additions to the Umon sources will be pushed accordingly.
    157157
     158* June 23: A set of patches were submitted recently on umon-devel@ that fix up the BBB port as well as the main Umon sources to allow Umon to be built successfully.  Another set of patches were also submitted that removed and replaced any irrelevant code in the BBB port.  The Umon command line has been reached, but functionality is still limited.  Executing some of the commands results in a data abort exception and after a substantial amount of debugging, the root cause of the problem has been determined.  A multitude of solutions were proposed and formulated, but the best solution is to transition to using the RTEMS compiler instead of the default arm cross-compiler toolset that is used to build Umon.  This transition will not only provide the possibility of eradicating the issues we were facing, but also to prevent any issues and complexities that could arise if we chose to transition to the RTEMS toolset later on.  Expanding on the premise stated, one thing to note about this transition is that it is an attempt to see if the issues regarding the data abort exception would be rectified.  As a result, I will now look into getting the Umon sources to be built using the RTEMS toolset.  Once Umon can be built using the RTEMS toolset, a patch will be developed to reflect these changes.    Furthermore, the previous set of patches have already been tested by Ed and now only requires some improvements, especially in the format of the code, and it should be ready to be merged with the main Umon sources.
     159
    158160== Sujay Raj ==
    159161