Changes between Version 154 and Version 155 of GSoC/2015


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Timestamp:
Jun 16, 2015, 5:13:44 PM (4 years ago)
Author:
Jarielle Catbagan
Comment:

Added status update for June 16, 2015

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  • GSoC/2015

    v154 v155  
    145145* June 9: The previous Umon image that was built was using the previous Umon 1.19 sources.  The new Umon source tree, which was obtained from the RTEMS git repos, is stripped of any code that would conflict with the licenses involved.  During the process where code was being removed, the directory/file structure of the new Umon source tree was shifted around to the point where a Umon image cannot be built immediately.  After performing the necessary modifications, the basic Umon image that boots from UART and was built from the Umon 1.19 sources can now be built with the new Umon source tree.  I have also looked more extensively in the initialization that Umon undergoes.  Umon does the minimum system intializations with the ultimate goal of presenting the Umon command line to the user.  As mentioned in the previous status update, in the context of the AM335x/Beaglebone Black, program execution first starts at rom_reset.S.  This contains the low-level mechanisms to initialize the system.  From here, a jump to the first C function start() is performed.  The general order of function invocation after start() is umonBssinit() -> init0() -> init1() -> init2() -> reginit() -> init3() before finally reaching CommandLoop() where the Umon command line is presented to the user.  Getting to this point is the main goal.  Since I am approaching the porting process with a top-down approach, the first step would be getting umonBssInit() to function properly.  Delving into the specifics of this function, it can be seen that it manipulates the memory location whose base address is 0x80000000.  Referring to the AM335x TRM, this is the start location of the external DDR3 SDRAM.  As of right now the main focus is performing the necessary configurations to get the external DDR3 SDRAM working before proceeding to modifying the next initialization functions along the chain previously specified.
    146146
     147* June 16: Since the last status update, I elaborated extensively the approach that I am taking in porting Umon as well as the fundamentals of DDR3 SDRAMs which can be found in my blog.  I have also consolidated all the necessary information that pertain to the composition, operation, and requirements of DDR3 and I am currently implementing the DDR3 configuration in rom_reset.S.  The BBB that I have has a 512MB DDR3 SDRAM, which is the D2516EC4BXGGB from Kingston, and I have already familiarized myself with the parameters of the DDR3 as it is required during the DDR3 configuration.  The memory subsystem on the AM335x, and subsequently on the BBB, that interfaces with the DDR3 SDRAM is the EMIF subsystem as specified in section 7.3 in the AM335x TRM.  Fortunately, TI has a dedicated wiki that provides tips and insights on the configuration of these registers within the EMIF subsystem in order to interface with DDR3.  There is also essential information in the JEDEC DDR3 Standard specification, in particular section 3.3.1, as it concisely summaries the sequence of steps required in order to reset and initialize DDR3 properly.  As a result, this is also utilized as reference for the current DDR3 implementation effort.  There are also the DDR PHY registers that must be configured accordingly based on the characteristics of the board where the DDR3 exists in order to ensure that proper timing is performed for all DDR transactions.  Additionally, the clocks going into the DDR memory must also be configured as specified in section 7.3.3.2 in the AM335x TRM.  The information that will be utilized to configure the DDR clocks is in section 8.1.6.11 in the AM335x TRM as well.  Once the DDR3 configuration is implemented, a simple test that I will be performing to ensure that the DDR3 is setup properly is by manipulating predetermined values within the DDR3 memory range and then outputting the values through UART0.  This memory range of the EMIF subsystem, and as a result it is also the memory that can be allocated to DDR3, is 0x80000000 - 0xBFFFFFFF.  This is equivalent to 1GB.  The modifications/additions to the Umon sources will be pushed accordingly.
     148
    147149== Sujay Raj ==
    148150