93 | | * May 19: Functional Pi 2. Have run benchmarks. I have been referring to TRMs for details. For next week, its completely identifying cache configurations and testing. Resolve issue faced with respect to scu implementation. |
| 93 | * May 19: Functional Pi 2. Have run benchmarks. I have been referring to TRMs for details. For next week, its completely identifying cache configurations and testing. Resolve issue faced with respect to scu implementation. |
| 94 | |
| 95 | * May 26: Looks like cache/mmu setup has been identified, except enabling maintenance operations. Start implementation and subsequent testing. Resolved SCU related issue. Started work with bsp hooks, first with hook 0. Identify common code with existing cortex-A9. |