Changes between Version 64 and Version 65 of Developer/SMP
- Timestamp:
- 04/17/14 18:09:56 (10 years ago)
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Developer/SMP
v64 v65 331 331 332 332 333 SMP locks are implemented as a ticket lock using CPU architecture specific atomic operations. 333 SMP locks are implemented as a ticket lock using CPU architecture specific atomic operations. The SMP locks use a local context to be able to use scalable lock implementations like the Mellor-Crummey and Scotty (MCS) queue-based locks. 334 334 == Future Directions == 335 335 336 336 337 * Use a local context to be able to use scalable lock implementations like the Mellor-Crummey and Scotty (MCS) queue-based locks. 338 * Introduce read-write locks. Use phase-fair read-write lock implementation. This can be used for example by the time management code. The system time may be read frequently, but updates are infrequent. 337 Introduce read-write locks. Use phase-fair read-write lock implementation. This can be used for example by the time management code. The system time may be read frequently, but updates are infrequent. 339 338 = ISR Locks = 340 339 … … 1505 1504 disable/enable). This simplifies them considerable. The thread queue 1506 1505 operations must be performed under the SMP lock of the object. The drawback is 1507 that the time of disabled interrupts increases. The FIFO thread queue 1508 o 1506 that the time of disabled interrupts increases. The FIFO thread