Changes between Version 46 and Version 47 of Developer/SMP


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Timestamp:
Mar 3, 2014, 7:54:07 PM (6 years ago)
Author:
Sh
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/* Requirements */ Add link

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  • Developer/SMP

    v46 v47  
    1818  *  Atomic operations and fences shall be used to implement higher-level synchronization primitives.
    1919  *  An SMP lock which ensures mutual exclusion and FIFO ordering shall be provided.
    20   *  An SMP read-write lock shall be provided which offers phase-fair ordering <ref name="BrandenburgAnderson2010">B. Brandenburg and J. H. Anderson, Spin-Based Reader-Writer Synchronization for Multiprocessor Real-Time Systems, July 2010.</ref>.
     20  *  An SMP read-write lock shall be provided which offers phase-fair ordering <ref name="BrandenburgAnderson2010">[http://www.mpi-sws.org/~bbb/papers/pdf/rtsj11.pdf Björn B. Brandenburg and James H. Anderson, Spin-Based Reader-Writer Synchronization for Multiprocessor Real-Time Systems, July 2010.]</ref>.
    2121  *  A re-usable SMP barrier shall be provided.
    2222  *  SMP synchronization primitives may execute infinitely without progress in case other processors execute erroneous code.
     
    15121512current processor, but without the per-processor lock acquired (to prevent lock
    15131513order reversal problems and keep the interrupt latency small).  For this we
    1514 introduce a post-switch action chain (PSAC).  Each thread will hav
     1514intr