8 | | {| border="1" style="margin: 1em auto 1em auto;text-align: center;" |
9 | | |+ |
10 | | |- |
11 | | |'''Architecture''' || '''Target CPU''' || '''RTEMS SMP''' || '''atomic-hardware''' || '''atomic-instruction''' || '''memory-ordering''' |
12 | | |- |
13 | | | X86 || i386 || Yes || Yes || cmpxchg || Stronger |
14 | | |- |
15 | | | PowerPC || powerpc || No || Yes || lwarx/stwcx || Weaker |
16 | | |- |
17 | | | SPARC (V7-V8) || sparc || No || Yes || ldstub/swap/cas(optional) || Stronger (TSO-mode) |
18 | | |- |
19 | | | SPARC V9 || sparc64 || No || Yes || ldstub/swap/cas || Stronger (TSO-mode) |
20 | | |- |
21 | | | MIPS || mips || No || Yes || ll/sc || Weaker |
22 | | |- |
23 | | | ARM || arm || No || Yes (V6 above) || ldstub/swap (V6 above) || Weaker |
24 | | |- |
25 | | | M68K || m68k || No || Yes || cad/cas32/tas || |
26 | | |- |
27 | | | Blackfin || bfin || No || no || no || |
28 | | |- |
29 | | | SH || sh || No || Yes || || |
30 | | |- |
31 | | | Lattice Mico32 || lm32 || || || || |
32 | | |- |
33 | | | Altera NIOS II || nios2 || || || || |
34 | | |- |
35 | | |} |
| 8 | |
| 9 | || '''Architecture''' || '''Target CPU''' || '''RTEMS SMP''' || '''atomic-hardware''' || '''atomic-instruction''' || '''memory-ordering''' || |
| 10 | || X86 || i386 || Yes || Yes || cmpxchg || Stronger || |
| 11 | || PowerPC || powerpc || No || Yes || lwarx/stwcx || Weaker || |
| 12 | || SPARC (V7-V8) || sparc || No || Yes || ldstub/swap/cas(optional) || Stronger (TSO-mode) || |
| 13 | || SPARC V9 || sparc64 || No || Yes || ldstub/swap/cas || Stronger (TSO-mode) || |
| 14 | || MIPS || mips || No || Yes || ll/sc || Weaker || |
| 15 | || ARM || arm || No || Yes (V6 above) || ldstub/swap (V6 above) || Weaker || |
| 16 | || M68K || m68k || No || Yes || cad/cas32/tas || || |
| 17 | || Blackfin || bfin || No || no || no || || |
| 18 | || SH || sh || No || Yes || || || |
| 19 | || Lattice Mico32 || lm32 || || || || || |
| 20 | || Altera NIOS II || nios2 || || || || || |
| 21 | |