Version 2 (modified by Chris Johns, on Jan 7, 2016 at 4:48:25 AM) (diff)

Fix spelling.


An RTEMS Architecture is an instruction set architecture (ISA) the RTEMS kernel and tools support. An instruction set architecture may contain a number of variations supported by a number of processor families. The processors maybe common to a single manufacture or many manufacturers may produce processors that implement the instruction set. RTEMS follows the ISA architecture model GCC provides. GCC supports the ISA variations using multlibs. A multilb GCC architecture has a number of libraries of code, one for each ISA variant.

Each RTEMS Architecture has a number of RTEMS Board Support Packages (BSPs). The BSP configuration determines the specific ISA variant to use as well as the specific processor features.

RTEMS Architecture Tiers

The RTEMS project supports RTEMS Architecture Tiers. Each architecture resided in one of the numbered tiers. The tiers are number 1 to 4 where Tier 1 is the highest tier and Tier 4 is the lowest. Architectures move between tiers based on the level of support and the level of testing that is performed. An architecture requires continual testing and reporting of test results to maintain a tier level. The RTEMS Project's continuous integration testing program continually monitors and reports the test results.

The RTEMS Architecture Tier system provides a defined way to determine the state of an architecture in RTEMS. Architectures age and support for them drops off and the RTEMS Project needs a way to determine if an architecture should stay and be supported or depreciated and removed. The tier system also provides users with a clear understand of the state of an architecture in RTEMS, often useful when deciding on a processor for a new project. It can also let a user know the RTEMS Project needs support to maintain a specific architecture. Access to hardware to perform testing is a large and complex undertaking and the RTEMS Project is always looking for user support and help. If you can help please contact someone and let us know.

Tier 1

Tier 1 is the highest tier level and requires testing on real hardware. Simulation or virtual machine can be used to speed up testing if the simulator testing results correlate to the hardware testing.

  1. All commits must build on all tier 1 architectures.
  2. There shall be no test regressions.
  3. There must be a supported BSP that provides:
    1. Hardware testing. This is real hardware based testing.
    2. Simulator testing. This is testing with an instruction simulator or suitable virtual machine.

Tier 2

Tier 3

Tier 4