Changes between Version 4 and Version 5 of Debugging/OpenOCD/Xilinx_Zynq


Ignore:
Timestamp:
Jan 14, 2016, 9:24:44 PM (3 years ago)
Author:
Chris Johns
Comment:

Add L2 cache control and masking the ISR set up.

Legend:

Unmodified
Added
Removed
Modified
  • Debugging/OpenOCD/Xilinx_Zynq

    v4 v5  
    245245}
    246246
     247proc zynq_rtems_setup { } {
     248    cache_config l2x 0xF8F02000 8
     249    cortex_a maskisr on
     250}
     251
    247252proc zynq_restart { wait } {
    248253    global _SMP
     
    282287    targets $target0
    283288    halt
     289    zynq_rtems_setup
    284290}
    285291