Changes between Version 4 and Version 5 of Debugging/OpenOCD/Xilinx_Zynq

Timestamp:

01/14/16 21:24:44 (8 years ago)

Author:

Chris Johns

Comment:

Add L2 cache control and masking the ISR set up.

Debugging/OpenOCD/Xilinx_Zynq

@@ -245 +245 @@
 }
 
+proc zynq_rtems_setup { } {
+    cache_config l2x 0xF8F02000 8
+    cortex_a maskisr on
+}
+
 proc zynq_restart { wait } {
     global _SMP
@@ -282 +287 @@
     targets $target0
     halt
+    zynq_rtems_setup
 }