Changes between Version 3 and Version 4 of Debugging/OpenOCD/Xilinx_Zynq

Timestamp:

08/14/15 15:26:19 (9 years ago)

Author:

Ric Claus

Comment:

--

Debugging/OpenOCD/Xilinx_Zynq

@@ -7 +7 @@
 Xilinx define the JTAG access to the Zynq part with a 14-pin header while suitable adaptors such as the Flyswatter2 have the standard ARM 20pin header. You can buy from Avnet a [http://www.em.avnet.com/en-us/design/drc/Pages/ZedBoard-Processor-Debug-Adapter.aspx  ZedBoard Processor Debug Adapter].
 
-JTAG access to the Zynq only operates if the board is in a suitable JTAG mode and it is not in a secure boot mode. Please refer to the Xilinx Zynq-7000 Technical Reference Manual and any user manul for your hardware for details on how to set the board's mode into JTAG.
+JTAG access to the Zynq only operates if the board is in a suitable JTAG mode and it is not in a secure boot mode. Please refer to the Xilinx Zynq-7000 Technical Reference Manual and any user manual for your hardware for details on how to set the board's mode into JTAG.
 
 == Xilinx SDK PS7 Initialisation ==
@@ -18 +18 @@
 #
 
-proc mrd { addr } {
-    mem2array x 32 $addr 1
-    return $x(0)
+proc mrd { args } {
+    if {[llength $args] == 0} {
+        echo "mrd address \[count \[w|h|b\]\]"
+        echo "    Read <count> memory locations starting at <address>.  Defaults to one word."
+        return
+    }
+    set addr [lindex $args 0]
+    set count  1
+    set bits  32
+    if {[llength $args] > 1} {
+        set count [lindex $args 1]
+        if {[llength $args] > 2} {
+            switch [lindex $args 2] {
+                w       { set bits 32 }
+                h       { set bits 16 }
+                b       { set bits  8 }
+                default { set bits 32 }
+            }
+        }
+    }
+    mem2array x $bits $addr $count
+    set nibbles [expr {$bits / 4}]
+    set bytes   [expr {$bits / 8}]
+    set result  {}
+    foreach {idx elmt} $x {
+        append result [format "%08x:   %0*x\n" [expr {$addr + $idx * $bytes}] $nibbles $elmt]
+    }
+    return $result
 }
 
 proc mask_write { addr mask value } {
-    set curval "[mrd $addr]"
+    set curval "0x[string range [mrd $addr] end-8 end]"
     set maskedval [expr {$curval & ~$mask}]
     #echo "curval = [format 0x%08x $curval] maskedval = [format 0x%08x $maskedval]"
@@ -46 +71 @@
 }}}
 
-This file will allow you to run the TCL script from the Xilinx SDK using OpenOCD. There are some instances around some parts of the initialisation that may not work. Uncomment the `echo` lines, location the writes that fail and comment those out from your PS7 init TCL script.
+This file will allow you to run the TCL script from the Xilinx SDK using OpenOCD. There are some instances around some parts of the initialisation that may not work. Uncomment the `echo` lines, locate the writes that fail and comment those out from your PS7 init TCL script.
 
 The main purpose of this initialisation process is to get working clocks and DDR memory so you can load your code and run it.
@@ -52 +77 @@
 == First Stage Boot Loader Initialisation ==
 
-A second approach to initialisation is to use the FSBL. The FSBL contains the C version of the PS7 initialisation produced by the SDK. The FSBL should detect the mode is JTAG and place the ARM code in a state where JTAG access is enabled. To do this you create an OpenOCD TCL script that loads the FSBL as an ELF file into the OCM and run it, pause for a small amount of time then halt the ARM code. At this point in time the Zynq will be initialised and you can download your application into DDR RAM.
+A second approach to initialisation is to use the FSBL. The FSBL contains the C version of the PS7 initialisation produced by the SDK. The FSBL should detect the mode is JTAG and place the ARM code in a state where JTAG access is enabled. To do this you create an OpenOCD TCL script that loads the FSBL as an ELF file into the OCM and runs it, pauses for a small amount of time to let it complete and then halts the ARM code. At this point in time the Zynq will be initialised and you can download your application into DDR RAM.
 
 == Xilinx Zynq-7000 Configuration File ==
@@ -81 +106 @@
 } else {
     global _CHIPNAME
-    set _CHIPNAME zc706
+    set _CHIPNAME zynq
 }
 
@@ -102 +127 @@
 # PL Tap.
 #
-# ZC706 devices:
-#   0x03731093 - Eval board 1.1
+# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
+#   0x03731093 - ZC706 Eval board 1.1
 #   0x23731093 - ??
+#   0x23727093 - Zedboard Rev. C and D
 #
 # Set in your configuration file or board specific file.
@@ -120 +146 @@
 # CoreSight Debug Access Port
 #
-if { [info exists DAPTAPID] } {
+if { [info exists DAP_TAPID] } {
     set _DAP_TAPID $DAP_TAPID
 } else {
@@ -258 +284 @@
 }
 
-proc zynq_zc706_gdb_attach { target } {
+proc zynq_gdb_attach { target } {
     catch {
       halt
@@ -315 +341 @@
 == GDB Configuration ==
 
-This configuration allow you to commit into your repository a standard configuration placing the host specific configuration in your home directory.
+This configuration allows you to commit into your repository a standard configuration placing the host specific configuration in your home directory.
 
 Create a `$HOME/.gdbinit` file and place in it:
@@ -321 +347 @@
 {{{
 def zynq-connect
-  target remote :3334
+  target remote :3333
 end
 
@@ -367 +393 @@
 b bsp_reset
 
-tb main
+tb Init
 c
 }}}