Changes between Version 3 and Version 4 of Debugging/OpenOCD/Xilinx_Zynq


Ignore:
Timestamp:
Aug 14, 2015, 3:26:19 PM (5 years ago)
Author:
Ric Claus
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • Debugging/OpenOCD/Xilinx_Zynq

    v3 v4  
    77Xilinx define the JTAG access to the Zynq part with a 14-pin header while suitable adaptors such as the Flyswatter2 have the standard ARM 20pin header. You can buy from Avnet a [http://www.em.avnet.com/en-us/design/drc/Pages/ZedBoard-Processor-Debug-Adapter.aspx  ZedBoard Processor Debug Adapter].
    88
    9 JTAG access to the Zynq only operates if the board is in a suitable JTAG mode and it is not in a secure boot mode. Please refer to the Xilinx Zynq-7000 Technical Reference Manual and any user manul for your hardware for details on how to set the board's mode into JTAG.
     9JTAG access to the Zynq only operates if the board is in a suitable JTAG mode and it is not in a secure boot mode. Please refer to the Xilinx Zynq-7000 Technical Reference Manual and any user manual for your hardware for details on how to set the board's mode into JTAG.
    1010
    1111== Xilinx SDK PS7 Initialisation ==
     
    1818#
    1919
    20 proc mrd { addr } {
    21     mem2array x 32 $addr 1
    22     return $x(0)
     20proc mrd { args } {
     21    if {[llength $args] == 0} {
     22        echo "mrd address \[count \[w|h|b\]\]"
     23        echo "    Read <count> memory locations starting at <address>.  Defaults to one word."
     24        return
     25    }
     26    set addr [lindex $args 0]
     27    set count  1
     28    set bits  32
     29    if {[llength $args] > 1} {
     30        set count [lindex $args 1]
     31        if {[llength $args] > 2} {
     32            switch [lindex $args 2] {
     33                w       { set bits 32 }
     34                h       { set bits 16 }
     35                b       { set bits  8 }
     36                default { set bits 32 }
     37            }
     38        }
     39    }
     40    mem2array x $bits $addr $count
     41    set nibbles [expr {$bits / 4}]
     42    set bytes   [expr {$bits / 8}]
     43    set result  {}
     44    foreach {idx elmt} $x {
     45        append result [format "%08x:   %0*x\n" [expr {$addr + $idx * $bytes}] $nibbles $elmt]
     46    }
     47    return $result
    2348}
    2449
    2550proc mask_write { addr mask value } {
    26     set curval "[mrd $addr]"
     51    set curval "0x[string range [mrd $addr] end-8 end]"
    2752    set maskedval [expr {$curval & ~$mask}]
    2853    #echo "curval = [format 0x%08x $curval] maskedval = [format 0x%08x $maskedval]"
     
    4671}}}
    4772
    48 This file will allow you to run the TCL script from the Xilinx SDK using OpenOCD. There are some instances around some parts of the initialisation that may not work. Uncomment the `echo` lines, location the writes that fail and comment those out from your PS7 init TCL script.
     73This file will allow you to run the TCL script from the Xilinx SDK using OpenOCD. There are some instances around some parts of the initialisation that may not work. Uncomment the `echo` lines, locate the writes that fail and comment those out from your PS7 init TCL script.
    4974
    5075The main purpose of this initialisation process is to get working clocks and DDR memory so you can load your code and run it.
     
    5277== First Stage Boot Loader Initialisation ==
    5378
    54 A second approach to initialisation is to use the FSBL. The FSBL contains the C version of the PS7 initialisation produced by the SDK. The FSBL should detect the mode is JTAG and place the ARM code in a state where JTAG access is enabled. To do this you create an OpenOCD TCL script that loads the FSBL as an ELF file into the OCM and run it, pause for a small amount of time then halt the ARM code. At this point in time the Zynq will be initialised and you can download your application into DDR RAM.
     79A second approach to initialisation is to use the FSBL. The FSBL contains the C version of the PS7 initialisation produced by the SDK. The FSBL should detect the mode is JTAG and place the ARM code in a state where JTAG access is enabled. To do this you create an OpenOCD TCL script that loads the FSBL as an ELF file into the OCM and runs it, pauses for a small amount of time to let it complete and then halts the ARM code. At this point in time the Zynq will be initialised and you can download your application into DDR RAM.
    5580
    5681== Xilinx Zynq-7000 Configuration File ==
     
    81106} else {
    82107    global _CHIPNAME
    83     set _CHIPNAME zc706
     108    set _CHIPNAME zynq
    84109}
    85110
     
    102127# PL Tap.
    103128#
    104 # ZC706 devices:
    105 #   0x03731093 - Eval board 1.1
     129# See ug585 ZYNQ-7000 TRM PSS_IDCODE for how this number is constructed.
     130#   0x03731093 - ZC706 Eval board 1.1
    106131#   0x23731093 - ??
     132#   0x23727093 - Zedboard Rev. C and D
    107133#
    108134# Set in your configuration file or board specific file.
     
    120146# CoreSight Debug Access Port
    121147#
    122 if { [info exists DAPTAPID] } {
     148if { [info exists DAP_TAPID] } {
    123149    set _DAP_TAPID $DAP_TAPID
    124150} else {
     
    258284}
    259285
    260 proc zynq_zc706_gdb_attach { target } {
     286proc zynq_gdb_attach { target } {
    261287    catch {
    262288      halt
     
    315341== GDB Configuration ==
    316342
    317 This configuration allow you to commit into your repository a standard configuration placing the host specific configuration in your home directory.
     343This configuration allows you to commit into your repository a standard configuration placing the host specific configuration in your home directory.
    318344
    319345Create a `$HOME/.gdbinit` file and place in it:
     
    321347{{{
    322348def zynq-connect
    323   target remote :3334
     349  target remote :3333
    324350end
    325351
     
    367393b bsp_reset
    368394
    369 tb main
     395tb Init
    370396c
    371397}}}