cpu_asm multi-instruction sequence in branch slot warning

[gregory.menke]

Fixes gcc warning about instructions in branch delay slot when compiling cpu_asm.S. Warnings refered to multi-instruction sequences that load the address of dword counters into a register for later load/save. If the branch is taken, the sequences are partically executed, causing the destination registor to be partially loaded. This is not a problem because the branch target is going to load registers as it desires, overwriting the partial load. Fix is to add a nop after the branches, forcing the register loads out of the delay slot.

Release:
rtems-4.7

Environment:
All mips bsp's

[gregory.menke]

State-Changed-From-To: open->closed
State-Changed-Why: Committed as cpu_asm.S 1.36