SPARC/grlib - Registers definitions wrongly defined when there are reserved bits

[Daniel Páscoa]

With respect to RTEMS 6 (ESA-promoted RTEMS SMP Qualification Data Pack release 3), the following issues are observed:

File	Lines	Discrepancy
bsps\include\grlib\ftmctrl-regs.h	84; 86; 88; 91; 96;98; 101; 106; 109; 115; 120; 123	According to table 365 of page 294 of the GR740 User Manual (v.2.50), the register addresses are incorrectly defined.
bsps\include\grlib\grgpio-regs.h	225	According to table 406 of page 319 of the GR740 User Manual (v.2,50), the register address is incorrect;
bsps\include\grlib\dsu4-regs.h	435	According to table 538 of page 403 of the GR740 User Manual (v.2.5), the register address is incorrect according to the table but it is correct according to the table description.
bsps\include\grlib\gr1553b-regs.h	609	According to table 327 of page 259 of the GR740 User Manual (v.2.50), the register address is incorrect according to the table but it is correct according to the table description.
bsps\include\grlib\spwpnp-regs.h	151	According to table 213 of page 200 of the GR740 User Manual (v.2.5), the register address is incorrect according to the table but it is correct according to the table description.
bsps\include\grlib\spwrmap-regs.h	575; 591; 715; 787; 809	According to tables 191, 192, 199, 201, 202, respectively (to each identified line) starting on page 192 of the GR740 User Manual (v.2.5), the register addresses are incorrect according to the table but are correct according to the table description.

It seems that the generation of these registers definitions leads to incorrect bit definitions whenever there are reserved bits specified in the Gaisler User Manual.
Can you please double-check these cases?

Additional Notes:
This ticket was raised as an outcome of the Independent SW Verification and Validation (ISVV) for ESA-promoted RTEMS SMP Qualification Data Packs (​https://rtems-qual.io.esa.int). The original ISVV reference for this issue is RTEMS-SMP-CODE-VER-014.

[Sebastian Huber]

The DSU4[ITCB0] ITPOINTER field seems to be correct in the description. See also the GRIP manual.

[Sebastian Huber]

The RTELM - GR1553B RT Event Log mask register should be clarified by Gaisler.

[Sebastian Huber]

With respect to the

• Space Wire Plug-and-Play - Active Links

• Interrupt port mask (IPMASK)

• Port interrupt pending (PIP)

• Link running status (LRUNSTAT)

the register block definitions are actually from the GRIP manual. In the latest version, up to 31 links are supported.

[Sebastian Huber]

To be check by Gaisler:

• Space Wire Plug-and-Play - Device Vendor and Product ID

• Space Wire Plug-and-Play - Unit Vendor and Product ID

[Sebastian Huber <sebastian.huber@…>]

In a7c2836/rtems-central:

spec: Fix FTMCTRL - MCFG1 bit fields

There was an off by one error in all bit fields. Add the R flag.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 239d254/rtems-central:

spec: Fix GRGPIO - IRQMAP bit fields

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In dd6f100/rtems-central:

spec: Fix SpaceWire? RMAP - Product ID

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 4fdeb56/rtems-central:

spec: Expand SpaceWire? port bit fields

Use the maximum width supported by the SpaceWire? standard even if this
exceeds the configuration limits of a particular IP instance.

Update #4842.

[Joel Sherrill]

This will be closed before 6. Please clone for 7 if continued.

[Sebastian Huber <sebastian.huber@…>]

In d4c1301/rtems-central:

spec: Add GRCAN - CanTxIRQ

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In b46ff7e/rtems-central:

spec: Expand GRCLKGATE register bit fields

Use the maximum width supported by the GRLIB even if this exceeds the
configuration limits of a particular IP instance.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 89b89fe/rtems-central:

spec: Move GR740-specific register blocks

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In d6c4baf/rtems-central:

spec: Use GRLIB definition of GRSPW2

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In d077161/rtems-central:

spec: Remove obsolete register block

This register block was an incomplete duplicate of
spec:/dev/grlib/if/grspw2.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 5771560/rtems-central:

spec: Use GRLIB definition of GRSPWROUTER

Rename item to match with GRLIB naming.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In e56cecf5/rtems:

bsps/grlib: Fix FTMCTRL - MCFG1 bit fields

There was an off by one error in all bit fields. Add the R flag.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In b7eb7d1f/rtems:

bsps/grlib: Fix GRGPIO - IRQMAP bit fields

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 7575890/rtems:

bsps/grlib: Fix SpaceWire? RMAP - Product ID

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In fe232596/rtems:

bsps/grlib: Expand SpaceWire? port bit fields

Use the maximum width supported by the SpaceWire? standard even if this
exceeds the configuration limits of a particular IP instance.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 845422b/rtems:

bsps/grlib: Fix SPWTDP register name

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In e6427f1e/rtems:

bsps/grlib: Add GRCAN - CanTxIRQ

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 584be21/rtems:

bsps/grlib: Expand GRCLKGATE register bit fields

Use the maximum width supported by the GRLIB even if this exceeds the
configuration limits of a particular IP instance.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In cba956b/rtems:

bsps/grlib: Move GR740-specific registers

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 181d989/rtems:

bsps/grlib: Use GRLIB definition of GRSPW2

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 06f63154/rtems:

bsps/grlib: Remove obsolete header file

This header file was an incomplete duplicate of <grlib/grspw2-regs.h>.

Update #4842.

[Sebastian Huber <sebastian.huber@…>]

In 49ad450/rtems:

bsps/grlib: Use GRLIB definition of GRSPWROUTER

Rename parts to match with GRLIB naming.

Close #4842.