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#4735 assigned enhancement

riscv start.S for a single core on a multicore device

Reported by: Lucian-Raul Silistru Owned by: Needs Funding
Priority: normal Milestone: Indefinite
Component: arch/riscv Version: 5
Severity: normal Keywords:
Cc: Blocked By:


We have run into a use-case where we are running non-SMP RTEMS on a riscv device with multiple harts that are pulled out of reset at the same time. All cores run the same code as the boot hartid - with predictable results (same int stack, same bss, all call boot_card).

Is there a plan/desire to support blocking any non-boot harts in a WFI loop, even in non-SMP? Or an infinite loop or a similar loop to SMP (+ a WFI)?

I saw singlecore SMP (with multicore device) parks any unused cores in Idle.

Change History (2)

comment:1 Changed on 10/05/22 at 15:06:37 by Lucian-Raul Silistru

Summary: riscv start.S for a singlecore on a multicore deviceriscv start.S for a single core on a multicore device

comment:2 Changed on 10/07/22 at 04:25:54 by Sebastian Huber

Milestone: Indefinite
Owner: set to Needs Funding
Status: newassigned

This should be easy to support with a BSP option. For example, RISCV_START_BOOT_HARTID. If this option is defined and RTEMS_SMP is not defined, then start.S loops if the hardid is not equal to the value of RISCV_START_BOOT_HARTID.

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