#3832 assigned defect

ARM interrupt support does not allow handling of FPU exceptions

Reported by: Sebastian Huber Owned by: Sebastian Huber
Priority: normal Milestone: Indefinite
Component: arch/arm Version: 4.11
Severity: normal Keywords:
Cc: Blocked By:


Several ARM floating point units provide implementation defined means to signal floating point exceptions, e.g. division by zero. Some systems (e.g. Cortex-R5F based TMS570LC4357) signal FPU exceptions via an interrupt. In this case the signal handler may want to clear the relevant bits in the Floating-point Status and Control Register (FPSCR). The FPSCR is saved on the interrupt frame on the stack, see:


After the interrupt processing it is restored from the interrupt frame. This discards all modifications of the FPSCR done by the interrupt handler. We need a mechanism to allow FPU exception interrupt handlers to modify the FPSCR persistently.

  1. One option is to save the interrupt frame pointer or the pointer to the FPSCR value in the Per_CPU_Control. This needs extra instructions in the critical path of interrupt processing.
  1. Another option is to add the interrupt frame pointer as a parameter to the interrupt handlers. This would be an API change and introduce a small overhead for all interrupt handlers.
  1. The interrupt frame is saved in the non-volatile register r9 in the exception prologue. We can preserve this register via a global register variable defined in the module implementing bsp_interrupt_dispatch(). In the FPU interrupt handler, the global register variable for r9 can be used to access the FPSCR on the interrupt frame. This approach has no performance impact.

The proposed approach is (C). A header file should be added for ARM, which defines the global register variable, a structure representing the interrupt frame, and a function to get a pointer to the frame.

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