#3785 closed task (fixed)
Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA
Reported by: | pragnesh | Owned by: | |
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Priority: | normal | Milestone: | 5.1 |
Component: | arch/riscv | Version: | 5 |
Severity: | normal | Keywords: | #RISCV, #FREEDOME310, #ARTYA7 |
Cc: | Blocked By: | ||
Blocking: |
Description
Change History (9)
comment:1 Changed on 08/16/19 at 13:25:22 by Joel Sherrill
comment:2 Changed on 08/16/19 at 13:38:55 by pragnesh
Replying to Joel Sherrill:
Please update the description of this ticket to clarify. My questions include:
- Are you planning to submit a BSP variant for this or are you asking for one?
- Either way please link to the hardware, manuals, etc.
1) Are you planning to submit a BSP variant for this or are you asking for one?
I have already sent a patch for this new BSP varient (Freedom E310) to
devel@ rtems.org, I created this ticket so that i can give reference in the commit
message. i followed this https://devel.rtems.org/wiki/Developer/Contributing
Let me know, Is this a right procedure to submit a patch?
2) Either way please link to the hardware, manuals, etc.
I will update the same in description.
comment:3 Changed on 08/19/19 at 08:59:01 by pragnesh
Link for the hardware and manuals
- https://www.sifive.com/documentation (Freedom FE310-G002 Manual)
- https://www.digikey.com/eewiki/display/LOGIC/Digilent+Arty+A7+with+Xilinx+Artix-7+Implementing+SiFive+FE310+RISC-V
- https://sifive.cdn.prismic.io/sifive%2Fed96de35-065f-474c-a432-9f6a364af9c8_sifive-e310-arty-gettingstarted-v1.0.6.pdf
comment:8 Changed on 11/29/19 at 07:46:02 by Pragnesh Patel <pragnesh.patel@…>
comment:9 Changed on 12/12/19 at 17:19:47 by Joel Sherrill
Resolution: | → fixed |
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Status: | new → closed |
Closing. The BSP and user manual contents are merged. Thank you for submitting the BSP
Please update the description of this ticket to clarify. My questions include: