#3760 closed defect (fixed)

BBB MMU update crashes

Reported by: Chris Johns Owned by: Chris Johns <chrisj@…>
Priority: normal Milestone: 5.1
Component: arch/arm Version: 5
Severity: normal Keywords:
Cc: Blocked By:
Blocking:

Description

Calling arm_cp15_set_translation_table_entries() on a BBB (Cortex-A8) crashes in the call to arm_cp15_tlb_invalidate_entry_all_asids(). There is no HYP support in the BBB's A8. The cp15 register is documented in the A8 manual but the BBB device from TI does not have the support built in.

A check of the A8 doco from ARM says this is for use in HYP mode so should we be using without checking if HYP is supported and if it is active? I am also wondering if we use should be using it on the Zynq. I have no idea why the Zync (A9) does not complain, it may be ignoring the invalidate request.

While looking at this code I was wondering why we do not follow ARM's recommendation of 'break-make' updates of the TLB? I do not know we could support such a process because we may be asked to invalidate the entry for the text section we are running in to update it.

Note, following the other path in the call works on a BBB.

Change History (5)

comment:1 Changed on Jun 25, 2019 at 10:08:06 AM by Chris Johns

The implementation is:

ARM_CP15_TEXT_SECTION static inline void
arm_cp15_tlb_invalidate_entry_all_asids(const void *mva)
{
  ARM_SWITCH_REGISTERS;

  mva = ARM_CP15_TLB_PREPARE_MVA(mva);

  __asm__ volatile (
    ARM_SWITCH_TO_ARM
    "mcr p15, 0, %[mva], c8, c7, 3\n"
    ARM_SWITCH_BACK
    : ARM_SWITCH_OUTPUT
    : [mva] "r" (mva)
  );
}

The cp15 register c8, 0, c7, 3 is undefined for a Cortex-A8 (ARM's document DDI0334K p3-12). The conditional define in arm_cp15_set_translation_table_entries catches the Cortex-A8.

comment:2 Changed on Jun 25, 2019 at 10:42:44 AM by Sebastian Huber

Can the availability checked via a feature register at runtime?

comment:3 in reply to:  2 Changed on Jun 25, 2019 at 10:44:49 AM by Chris Johns

Replying to Sebastian Huber:

Can the availability checked via a feature register at runtime?

Yes I think so. The test can be for variant 3 or earlier for the Cortex-A8 and 4 or higher for Cortex-A9 or later.

comment:4 Changed on Jul 30, 2019 at 10:38:00 PM by Chris Johns <chrisj@…>

Owner: set to Chris Johns <chrisj@…>
Resolution: fixed
Status: newclosed

In 98d6792/rtems:

arm: Select the TLB invalidate based on the core's Id variant.

Closes #3760

comment:5 Changed on Aug 12, 2019 at 11:01:20 PM by Chris Johns <chrisj@…>

In 15b6f44d/rtems:

arm/tlb: Fix the MP affinity check to invalidate ASIDs.

  • The TI's CortexA7 MP MPIDR register returns 0

Updates #3760

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