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#3173 closed defect (fixed)

XIlinx AXI I2C driver IP race condition causes clock glitch.

Reported by: Chris Johns Owned by: Chris Johns
Priority: normal Milestone: 5.1
Component: arch/arm Version: 5
Severity: normal Keywords: I2C XIlinx AXI
Cc: Blocked By:
Blocking:

Description

The Xilinx AXI I2C IP has a race condition when the PIRQ read FIFO level is reached and the clock is throttling.

Change History (3)

comment:1 Changed on 10/16/17 at 06:18:44 by Sebastian Huber

Component: scorearch/arm

comment:2 Changed on 11/09/17 at 06:27:14 by Sebastian Huber

Milestone: 4.12.05.1

Milestone renamed

comment:3 Changed on 02/01/18 at 04:00:19 by Chris Johns <chrisj@…>

Resolution: fixed
Status: assignedclosed

In [changeset:"05015dc1886d08e9f9f3ed453688c52cebd4cc3f/rtems" 05015dc1/rtems]:

Xilinx AXI I2C driver IP race condition causes clock glitch.

Setting the PIRQ to 0 before reading the data produces a short clock pulse.
Moving the write to after reading the data fixes the issue.

Close #3173

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