#3109 closed enhancement (fixed)

Add RISC-V support

Reported by: Sebastian Huber Owned by: Hesham Almatary
Priority: normal Milestone: 5.1
Component: arch/riscv Version: 5
Severity: normal Keywords:
Cc: Blocked By:


Add RISC-V 32-bit tool chain to RSB consisting of Binutils, GCC, Newlib and GDB. Add CPU port and a basic simulator BSP.

Change History (11)

comment:1 Changed on Aug 23, 2017 at 5:21:49 AM by Sebastian Huber <sebastian.huber@…>

In e960835/rtems-source-builder:

4.12: Add riscv32 to all

Update #3109.

comment:2 Changed on Oct 25, 2017 at 11:20:39 PM by Hesham Almatary

Owner: set to Hesham Almatary
Status: newaccepted

comment:3 Changed on Oct 26, 2017 at 5:21:42 AM by Hesham Almatary

Summary: Add RISC-V 32-bit supportAdd RISC-V support

Account for 64-bit RISC-V

comment:4 Changed on Oct 27, 2017 at 5:45:00 AM by Hesham Almatary <heshamelmatary@…>

In 5bd4aa6/rtems-source-builder:

RSB - Add support for RISC-V RV64 (64-bit) toolchain v2

Update #3109

comment:5 Changed on Oct 28, 2017 at 7:01:25 AM by Hesham Almatary <heshamelmatary@…>

In e274bdf/rtems-source-builder:

RSB - RISC-V: Add scripts to build RISC-V's simulator

Update #3109

comment:6 Changed on Oct 28, 2017 at 7:11:34 AM by Hesham Almatary <heshamelmatary@…>

In 35b9c0c/rtems-tools:

Tester - RISC-V: Add spike simulator and scripts/bsp for riscv ports

Update #3109

comment:7 Changed on Oct 28, 2017 at 7:42:52 AM by Hesham Almatary <hesham@…>

In 6d85e05/rtems:

bsp: Add new riscv_generic bsp v3

  • Only runs/tested on simulator/spike.
  • Ticker, hello, capture work proprely
  • Tested via RTEMS Tester, Passed: 525/565 (92%)

Update #3109

comment:8 Changed on Oct 28, 2017 at 12:07:52 PM by Sebastian Huber <sebastian.huber@…>

In cf614ec/rtems:

riscv32: Add missing preinstall.am

Update #3109.

comment:9 Changed on Oct 31, 2017 at 11:22:09 PM by Hesham Almatary <heshamelmatary@…>

In 8fa827c/rtems:

bsp: Make riscv_generic work for both riscv32 and riscv64 - v2

Update #3109

comment:10 Changed on Jan 4, 2018 at 6:19:47 AM by Sebastian Huber <sebastian.huber@…>

In 030ce68/rtems:

tests: Fix canonical-target-name.m4

Update #3109.

comment:11 Changed on Aug 24, 2018 at 5:13:10 AM by Sebastian Huber

Component: unspecifiedarch/riscv
Milestone: Indefinite5.1
Resolution: fixed
Status: acceptedclosed
Version: 5

Superseded by #3433, #3452, and #3453.

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