Opened on 08/23/17 at 05:20:45
Closed on 08/24/18 at 05:13:10
#3109 closed enhancement (fixed)
Add RISC-V support
Reported by: | Sebastian Huber | Owned by: | Hesham Almatary |
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Priority: | normal | Milestone: | 5.1 |
Component: | arch/riscv | Version: | 5 |
Severity: | normal | Keywords: | |
Cc: | Blocked By: | ||
Blocking: |
Description
Add RISC-V 32-bit tool chain to RSB consisting of Binutils, GCC, Newlib and GDB. Add CPU port and a basic simulator BSP.
Change History (11)
comment:1 Changed on 08/23/17 at 05:21:49 by Sebastian Huber <sebastian.huber@…>
comment:2 Changed on 10/25/17 at 23:20:39 by Hesham Almatary
Owner: | set to Hesham Almatary |
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Status: | new → accepted |
comment:3 Changed on 10/26/17 at 05:21:42 by Hesham Almatary
Summary: | Add RISC-V 32-bit support → Add RISC-V support |
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Account for 64-bit RISC-V
comment:4 Changed on 10/27/17 at 05:45:00 by Hesham Almatary <heshamelmatary@…>
comment:5 Changed on 10/28/17 at 07:01:25 by Hesham Almatary <heshamelmatary@…>
comment:6 Changed on 10/28/17 at 07:11:34 by Hesham Almatary <heshamelmatary@…>
comment:11 Changed on 08/24/18 at 05:13:10 by Sebastian Huber
Component: | unspecified → arch/riscv |
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Milestone: | Indefinite → 5.1 |
Resolution: | → fixed |
Status: | accepted → closed |
Version: | → 5 |
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