#2902 new project

Port RTEMS to Microblaze

Reported by: Tanu Hari Dixit Owned by: Joel Sherrill
Priority: normal Milestone: Indefinite
Component: bsps Version:
Severity: normal Keywords: SoC, BSP
Cc: Blocked By:

Description (last modified by Joel Sherrill)

Port RTEMS to Microblaze

Students: Past, Present, and Potential Students

Status: The tools build from RSB properly, but GDB is not compatible with current XDM (Xilinx Debugging Module), Xilinx GDB version is working fine.

Introduction: A new architecture port, not just BSP. Include a BSP for GDB simulator. Also needs BSP for more complete HW on simulator.

Goal: Update the preliminary Microblaze port, complete clock timer support, merge into RTEMS, and continue to improve the BSP/port.

Some work has been initiated here [1] (By Joel Sherrill and Hesham ALMatary) to get hello world working. It has been tested on Atlys FPGA board [2]. The BSP can run virtually on every FPGA board the Xilinx tools support building MicroBlaze? on.

The work will need to be updated against the current RTEMS version and tools and then completed. There are multiple boards supported by qemu-system-microblaze. One of these should be suitable for completing the port including interrupts. It will require investigation to know if qemu includes networking support for the Microblaze but this is likely.


Change History (5)

comment:1 Changed on Feb 6, 2017 at 4:02:32 AM by Chris Johns

Type: enhancementproject

comment:2 Changed on Mar 2, 2017 at 8:45:40 PM by Gedare Bloom

Keywords: BSP added

comment:3 Changed on Aug 14, 2017 at 12:04:23 AM by Chris Johns

Version: 4.11

comment:4 Changed on Jan 14, 2020 at 8:53:20 PM by Gedare Bloom

Description: modified (diff)

comment:5 Changed on May 29, 2020 at 12:58:33 PM by Joel Sherrill

Description: modified (diff)
Note: See TracTickets for help on using tickets.