Thread dispatch via interrupt is broken at least on ARM and PowerPC

[Sebastian Huber]

The ARM and PowerPC interrupt epilogues call _Thread_Dispatch() with interrupts disabled (counter example: SPARC).

On SMP configurations, since inter-processor interrupts set the thread dispatch necessary indicator this prevents a thread dispatch notification in post-switch handlers (which all run with interrupts disabled).

On all configurations, this is a serious issue for the interrupt latency.

[Sebastian Huber <sebastian.huber@…>]

In 8d5b03802e99e581c360e9a2cf67856596ec824c/rtems:

score: Workaround for #2751

The ARM and PowerPC interrupt epilogues call _Thread_Dispatch() with
interrupts disabled (counter example: SPARC).

On SMP configurations, since inter-processor interrupts set the thread
dispatch necessary indicator this prevents a thread dispatch
notification in post-switch handlers (which all run with interrupts
disabled).

On all configurations, this is a serious issue for the interrupt
latency.

Update #2751

[Sebastian Huber <sebastian.huber@…>]

In d78d5294cd076b48160e12c2f52a940d783b4dac/rtems:

score: Add and use _Thread_Dispatch_direct()

This function is useful for operations which synchronously block, e.g.
self restart, self deletion, yield, sleep. It helps to detect if these
operations are called in the wrong context. Since the thread dispatch
necessary indicator is not used, this is more robust in some SMP
situations.

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In 2072dd242f269ca7d3d14b8f4e2830f15e85e555/rtems:

score: Add Per_CPU_Control::isr_dispatch_disable

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In c11ac2d59dce04b189948dd851b1f1eb6f9a4a52/rtems:

sparc: Use Per_CPU_Control::isr_dispatch_disable

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In d59585db26ea30d23a0d112212cf4b42d01e73fc/rtems:

arm: Use Per_CPU_Control::isr_dispatch_disable

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In 7ce60b378dcf732e1467dcb7664a94824ac608c7/rtems:

powerpc: Use Per_CPU_Control::isr_dispatch_disable

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In 4e2bc0a308104d96b60d8af1a0c5bcff99fe1564/rtems:

arm: Fix Thumb-1 targets

We cannot use the MRS or MSR instructions in Thumb-1 mode. Stay in ARM
mode for the Thumb-1 targets during interrupt low-level processing.

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In 1d18a9027d04625306d08c4971a7735ce4b7e9f7/rtems:

arm: Fix _ARMV4_Exception_interrupt

Use the right register to determine if a thread dispatch is allowed and
necessary.

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In 4b5ff47d159872ef9e1096713fd68367f4640576/rtems:

score: Fix interrupt profiling

Callers of _Thread_Do_dispatch() must have a valid
Per_CPU_Control::Stats::thread_dispatch_disabled_instant.

Call _Profiling_Outer_most_interrupt_entry_and_exit() with the interrupt
stack to not exceed Per_CPU_Control::Interrupt_frame.

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In f65dcc712ab7ff1fb36da4254b4383f4fc5eb459/rtems:

score: Fix ARM and PowerPC context initialization

Update #2751.

[Sebastian Huber <sebastian.huber@…>]

In 436a4b384b70b4b050d5c5967c169a2b79f90042/rtems:

smptests/smpsignal01: Check signal ISR level

Close #2751.

[Sebastian Huber <sebastian.huber@…>]

In cd3d747/rtems:

arm: Optimize context switch

Set CPU_ENABLE_ROBUST_THREAD_DISPATCH to TRUE. In this case the
interrupts are always enabled during a context switch even after
interrupt processing (see #2751). Remove the CPSR from the context
control since it contains only volatile bits.

Close #2954.

[Sebastian Huber <sebastian.huber@…>]

In d5c8756/rtems:

arm: Fix profiling support of Thumb-1 targets

Update #2751.

[Sebastian Huber]

Milestone renamed

[Sebastian Huber <sebastian.huber@…>]

In 9704d86f/rtems:

riscv: Enable interrupts during dispatch after ISR

The code sequence is derived from the ARM code
(see _ARMV4_Exception_interrupt).

Update #2751.
Update #3433.