#2460 closed defect (duplicate)

arm-gic.h - GIC_ID_TO_TWO_BITS_REG_OFFSET(id) incorrectly defined

Reported by: Adit Owned by:
Priority: normal Milestone: 4.11.3
Component: arch/arm Version: 4.11
Severity: normal Keywords:
Cc: Blocked By:


This bug pertains to the ARM Generic Interrupt Controller (GIC) register utility functions in


The following routines all use the macro GIC_ID_TO_TWO_BITS_REG_OFFSET(id):


These routines set the GIC_ICFGRn set of registers. These registers have 2-bit bit fields. Let's take the trigger mode routines as an example of the bug, but it applies to the handling mode as well. The GIC specification from ARM states that for a particular interrupt ID m the register n and bit field F is found by:

n = m DIV 16
F = m MOD 16

And the bit location in register n is defined as [2F+1:2F]. However, the macro GIC_ID_TO_TWO_BITS_REG_OFFSET(id) and the routines that use it, set bits [F+1:F].

I have tested this by using the set_trigger_mode routine to set an interrupt to be edge triggered, but the correct bit does not get set, and the interrupt still behaves in a level triggered fashion. When I adjust the macro to have a << 1 it works correctly.

If someone can verify my logic at least, then I can submit a tested patch.

Attachments (1)

Change History (7)

comment:1 Changed on Nov 10, 2015 at 7:16:01 AM by Sebastian Huber

Yes, please send a patch to devel(at)rtems.org and add "Close #2460." to the commit message.

Last edited on Nov 10, 2015 at 7:16:55 AM by Sebastian Huber (previous) (diff)

comment:2 Changed on Jan 26, 2017 at 7:16:00 AM by Sebastian Huber


comment:3 Changed on Mar 23, 2017 at 1:04:45 AM by Chris Johns


The 4.11.2 milestone is closing.

comment:4 Changed on Feb 5, 2018 at 4:40:23 AM by Chris Johns

Milestone: 4.11.3Indefinite

Requires funding.

comment:5 Changed on Feb 5, 2018 at 7:48:15 AM by Sebastian Huber

Milestone: Indefinite4.11.3
Resolution: duplicate
Status: newclosed

Duplicate of #3002.

comment:6 Changed on Feb 5, 2018 at 7:59:59 AM by Sebastian Huber

Component: bspsarch/arm
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