#213 closed enhancement (fixed)

Support for 7400 PowerPC (AKA G4); misc enhancements for 60x family

Reported by: strauman Owned by: Joel Sherrill
Priority: lowest Milestone: 2
Component: score Version: unknown
Severity: minor Keywords:
Cc: bugs@… Blocked By:


  • support for the MPC74000 (AKA G4); there is no AltiVec? support yet, however.
  • the cache flushing assembly code uses hardware-flush on the G4. Also, a couple of hardcoded numerical values were replaced by more readable symbolic constants.
  • extended interrupt-disabled code section to enclose the entire cache flush/invalidate procedure (as recommended by the book). This is not (latency) critical as it is only used by init code but prevents possible corruption.
  • Trivial page table support as been added. (1:1 effective-virtual-physical address mapping) (useful only on CPUs which feature hardware TLB replacement, i.e. >604). This allows for write-protecting memory regions, e.g. text/ro-data which makes catching corruptors a lot easier. It also frees one DBAT/IBAT and gives more flexibility for setting up address maps :-)
  • setdbat() allows changing BAT0 also (since the BSP may use a page table, BAT0 could be available...).
  • asm_setdbatX() violated the SVR ABI by using r20 as a scratch register; changed for r0
  • according to the book, a context synchronizing instruction is necessary prior to and after changing a DBAT -> isync added


Target: powerpc-rtems
Host: i386-linux


Attachments (1)

ppc7400.diff (49.9 KB) - added by strauman on 12/03/06 at 13:31:13.

Download all attachments as: .zip

Change History (2)

comment:1 Changed on 05/14/02 at 15:58:07 by Joel Sherrill

Status: assignedclosed

State-Changed-From-To: open->closed
State-Changed-Why: Patch applied. Thank you.

Note that I had to move the mods to shared/include/cpu.h
to their new locations as this file was removed and
dispersed as part of making the powerpc support multilib

Changed on 12/03/06 at 13:31:13 by strauman

Attachment: ppc7400.diff added


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