#2003 closed defect (worksforme)

Instruction cache problem in gen5200 bsps

Reported by: ktaylan Owned by: Sebastian Huber
Priority: normal Milestone: 4.10
Component: bsps Version: 4.10
Severity: major Keywords:
Cc: joel.sherrill@…, sebastian.huber@… Blocked By:
Blocking:

Description (last modified by Sebastian Huber)

There is a function called "cpu_init" in gen5200 bsp. In that function there is a code segment that enables instruction cache. However without settings BATs for instruction cache and settings some bits in HID0 register, instruction cache cannot be enabled. The only code that enables instruction cache in current function is;

msr = ppc_machine_state_register();

msr |= MSR_IR;

ppc_set_machine_state_register(msr);

But additionally the below code should be added and BATs for instruction cache should be set. In the attachment there is a code for updated cpuinit.c file. This is done for Phytec MPC5200B I/O CPU module (which is not defined in current bsp list. I hope i will propose to add this bsp codes to upcoming releases)

PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICE | HID0_ICFI);
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICFI);

NOTE: Without enabling instruction cache performance drops 4-5 times.

Attachments (1)

cpuinit.c (11.6 KB) - added by ktaylan on Feb 1, 2012 at 5:48:02 AM.
CPU init. functions in gen5200 bsps

Download all attachments as: .zip

Change History (7)

Changed on Feb 1, 2012 at 5:48:02 AM by ktaylan

Attachment: cpuinit.c added

CPU init. functions in gen5200 bsps

comment:1 Changed on Feb 1, 2012 at 12:12:00 PM by Sebastian Huber

Cc: Sebastian Huber added

comment:2 Changed on Feb 1, 2012 at 1:08:28 PM by Joel Sherrill

Owner: changed from Joel Sherrill to Sebastian Huber

comment:3 Changed on Feb 1, 2012 at 1:10:25 PM by Joel Sherrill

Cc: Joel Sherrill added

comment:4 Changed on Feb 6, 2012 at 7:32:14 AM by Sebastian Huber

The current setting is a bit coarse. The BSP sets HID0[ICE]. This means the instruction cache is available. Since we do not set the MSR[IR] bit, we use the default memory attributes (IBAT and MMU settings are ignored). By default the cache is on. See e300 core manual section
4.4.1 "Memory/Cache? Access Attributes (WIMG Bits)". We can of coarse enhance the BSP startup to set also the IBAT registers.

comment:5 Changed on Nov 21, 2014 at 12:35:29 PM by Sebastian Huber

Description: modified (diff)
Resolution: wontfix
Status: newclosed

comment:6 Changed on Dec 12, 2014 at 7:27:50 AM by Sebastian Huber

Description: modified (diff)
Milestone: 4.114.10
Resolution: worksforme
Status: newclosed
Note: See TracTickets for help on using tickets.