Opened on 02/01/12 at 05:46:32
Closed on 12/12/14 at 07:27:50
#2003 closed defect (worksforme)
Instruction cache problem in gen5200 bsps
Reported by: | ktaylan | Owned by: | Sebastian Huber |
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Priority: | normal | Milestone: | 4.10 |
Component: | bsps | Version: | 4.10 |
Severity: | major | Keywords: | |
Cc: | joel.sherrill@…, sebastian.huber@… | Blocked By: | |
Blocking: |
Description (last modified by Sebastian Huber)
There is a function called "cpu_init" in gen5200 bsp. In that function there is a code segment that enables instruction cache. However without settings BATs for instruction cache and settings some bits in HID0 register, instruction cache cannot be enabled. The only code that enables instruction cache in current function is;
msr = ppc_machine_state_register();
msr |= MSR_IR;
ppc_set_machine_state_register(msr);
But additionally the below code should be added and BATs for instruction cache should be set. In the attachment there is a code for updated cpuinit.c file. This is done for Phytec MPC5200B I/O CPU module (which is not defined in current bsp list. I hope i will propose to add this bsp codes to upcoming releases)
PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICE | HID0_ICFI);
PPC_CLEAR_SPECIAL_PURPOSE_REGISTER_BITS(HID0, HID0_ICFI);
NOTE: Without enabling instruction cache performance drops 4-5 times.
Attachments (1)
Change History (7)
Changed on 02/01/12 at 05:48:02 by ktaylan
comment:1 Changed on 02/01/12 at 12:12:00 by Sebastian Huber
Cc: | Sebastian Huber added |
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comment:2 Changed on 02/01/12 at 13:08:28 by Joel Sherrill
Owner: | changed from Joel Sherrill to Sebastian Huber |
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comment:3 Changed on 02/01/12 at 13:10:25 by Joel Sherrill
Cc: | Joel Sherrill added |
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comment:4 Changed on 02/06/12 at 07:32:14 by Sebastian Huber
The current setting is a bit coarse. The BSP sets HID0[ICE]. This means the instruction cache is available. Since we do not set the MSR[IR] bit, we use the default memory attributes (IBAT and MMU settings are ignored). By default the cache is on. See e300 core manual section
4.4.1 "Memory/Cache? Access Attributes (WIMG Bits)". We can of coarse enhance the BSP startup to set also the IBAT registers.
comment:5 Changed on 11/21/14 at 12:35:29 by Sebastian Huber
Description: | modified (diff) |
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Resolution: | → wontfix |
Status: | new → closed |
comment:6 Changed on 12/12/14 at 07:27:50 by Sebastian Huber
Description: | modified (diff) |
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Milestone: | 4.11 → 4.10 |
Resolution: | → worksforme |
Status: | new → closed |
CPU init. functions in gen5200 bsps