#1407 closed defect (fixed)

Thread dispatch after interrupt processing

Reported by: Sebastian Huber Owned by: thomas.doerfler
Priority: normal Milestone: 4.10
Component: score Version: 4.10
Severity: normal Keywords:
Cc: joel.sherrill@…, strauman@…, thomas.doerfler@…, chrisj@… Blocked By:
Blocking:

Description

A common task of interrupt handlers is to do a thread dispatch after the actual
interrupt processing. On many architectures this is done in assembler code
which lead recently to problems due to a data type size change, see also

https://www.rtems.org/bugzilla/show_bug.cgi?id=1385

On PowerPC we use a high-level function that does this job, so we are not affected by these kind of problems. The PowerPC implementation differs also functionally from various other architectures (for example ARM and m68k). The task of thread dispatching and signal handling should be architecture independent, so we have a bug either in the PowerPC exception handling or the other architectures.

To avoid these issues we should provide an architecture independent high level implementation. See also the attached patch.

Attachments (6)

isrthreaddispatch.patch (2.4 KB) - added by Sebastian Huber on Apr 30, 2009 at 8:44:29 AM.
_ISR_Thread_dispatch()
isr.patch (3.6 KB) - added by Sebastian Huber on Jul 13, 2009 at 1:52:52 PM.
Implementation
isr_v1.patch (3.6 KB) - added by Sebastian Huber on Jul 14, 2009 at 7:44:47 AM.
Fixed typo
isr_v2.patch (3.5 KB) - added by Sebastian Huber on Jul 15, 2009 at 11:01:56 AM.
Fixed comment
isr_v3.patch (3.7 KB) - added by thomas.doerfler on Jul 17, 2009 at 8:05:41 AM.
patch only activates the code, if the cpu arch needs it
isr_v4.patch (1.4 KB) - added by Sebastian Huber on Jul 17, 2009 at 2:02:28 PM.
Proposal

Download all attachments as: .zip

Change History (12)

Changed on Apr 30, 2009 at 8:44:29 AM by Sebastian Huber

Attachment: isrthreaddispatch.patch added

_ISR_Thread_dispatch()

Changed on Jul 13, 2009 at 1:52:52 PM by Sebastian Huber

Attachment: isr.patch added

Implementation

Changed on Jul 14, 2009 at 7:44:47 AM by Sebastian Huber

Attachment: isr_v1.patch added

Fixed typo

Changed on Jul 15, 2009 at 11:01:56 AM by Sebastian Huber

Attachment: isr_v2.patch added

Fixed comment

comment:1 Changed on Jul 15, 2009 at 11:01:56 AM by Sebastian Huber

attachments.isobsolete: 01, 1, 1

comment:2 Changed on Jul 17, 2009 at 8:04:18 AM by thomas.doerfler

Owner: changed from Joel Sherrill to thomas.doerfler
Status: newassigned, thomas.doerfler@embedded-brains.de

Changed on Jul 17, 2009 at 8:05:41 AM by thomas.doerfler

Attachment: isr_v3.patch added

patch only activates the code, if the cpu arch needs it

comment:3 Changed on Jul 17, 2009 at 8:14:36 AM by thomas.doerfler

Resolution: fixed
Status: assignedclosed

comment:4 Changed on Jul 17, 2009 at 12:53:24 PM by Joel Sherrill

Cc: Joel Sherrill added

Changed on Jul 17, 2009 at 2:02:28 PM by Sebastian Huber

Attachment: isr_v4.patch added

Proposal

comment:5 Changed on Jul 17, 2009 at 2:02:28 PM by Sebastian Huber

attachments.isobsolete: 01, 1

comment:6 Changed on Jul 22, 2009 at 12:46:27 AM by Chris Johns

I think the reason there are 2 conditions (_Context_Switch_necessary and _ISR_Signals_to_thread_executing) is a performance gain. I would not change the way this works.

If you signal a thread from an ISR that is currently running you can save the overhead of a context switch check. In this case the context switch loop is not entered and the post context switch check is run.

Back to this change. I do not see how it fits the m68k target. We only call _Thread_Dispatch when we know there is work to do _and_ in the case of the processors with a hardware stack register we need to play with the stack using asm. I like the current m68k code because these checks and exit path are in line in the cache and I suspect pipelined for those variants that support it. A call to _ISR_Thread_dispatch would stall the pipeline, require cache loads all for a couple of instructions only to do the same again for the _Thread_Dispatch call.

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