|
|
@49a88a7
|
09/15/23 06:21:21 |
Sebastian Huber |
score: Add _CPU_Get_TLS_thread_pointer()
Add …
|
|
|
@bcef89f2
|
05/19/23 06:18:25 |
Sebastian Huber |
Update company name
The embedded brains GmbH & Co. KG is the legal …
|
|
|
@e9a69c5
|
10/14/22 08:52:00 |
Sebastian Huber |
riscv: Move functions to avoid build issues
The …
|
|
|
@4c89fbcd
|
09/27/22 05:43:37 |
Sebastian Huber |
score: Add CPU_THREAD_LOCAL_STORAGE_VARIANT
Update #3835.
|
|
|
@6b0d3c9
|
09/19/22 13:00:26 |
padmarao.begari |
bsps/riscv: Add Microchip PolarFire? SoC BSP variant
The Microchip …
|
|
|
@a660e9dc
|
09/08/22 08:37:05 |
Sebastian Huber |
Do not use RTEMS_INLINE_ROUTINE
Directly use "static inline" which is …
|
|
|
@03e4d1e9
|
06/29/22 12:37:47 |
Sebastian Huber |
score: Add _CPU_Use_thread_local_storage()
At some point during …
|
|
|
@faaffbd9
|
02/25/22 16:45:06 |
Sebastian Huber |
riscv: Use zicsr architecture extension
This is required for ISA 2.0 …
|
|
|
@8b65b574
|
07/28/21 12:41:32 |
Sebastian Huber |
score: Canonicalize _CPU_Fatal_halt()
Move _CPU_Fatal_halt() …
|
|
|
@71f9098
|
03/27/19 09:38:56 |
andreas.dachsberger |
doxygen: score: Add RISC-V CPU architecture group
Update #3706.
5
|
|
|
@cfc9573
|
07/27/18 12:47:17 |
Sebastian Huber |
riscv: Rework CPU counter support
Update #3433.
5
|
|
|
@6b9ef09
|
07/20/18 08:57:59 |
Sebastian Huber |
riscv: Add CLINT and PLIC support
The CLINT and PLIC need some …
5
|
|
|
@8db3f0e
|
07/19/18 10:11:19 |
Sebastian Huber |
riscv: Rework exception handling
Remove …
5
|
|
|
@5694b0c
|
07/19/18 08:15:53 |
Sebastian Huber |
riscv: New CPU_Exception_frame
Use the CPU_Interrupt_frame for the …
5
|
|
|
@3a646426
|
07/19/18 10:53:34 |
Sebastian Huber |
score: Add _CPU_Instruction_illegal()
On some …
5
|
|
|
@b74353e
|
07/20/18 06:06:46 |
Sebastian Huber |
score: Add _CPU_Instruction_no_operation()
This helps to reduce the …
5
|
|
|
@42f2fdfd
|
07/20/18 05:56:43 |
Sebastian Huber |
score: Move context validation declarations
The context validation …
5
|
|
|
@e755782
|
07/03/18 07:54:47 |
Sebastian Huber |
riscv: Clear reservations
See also RISC-V User-Level ISA V2.3, …
5
|
|
|
@e07b51a7
|
07/02/18 13:21:36 |
Sebastian Huber |
riscv: Fix fcsr initialization
Update #3433.
5
|
|
|
@52352387
|
06/28/18 07:32:26 |
Sebastian Huber |
riscv: Add floating-point support
Update #3433.
5
|
|
|
@e43994d
|
06/27/18 08:05:50 |
Sebastian Huber |
riscv: Optimize context switch and interrupts
Save/restore …
5
|
|
|
@b706b4a
|
06/27/18 06:54:13 |
Sebastian Huber |
riscv: Remove mstatus from thread context
The mstatus register …
5
|
|
|
@9704d86f
|
06/26/18 06:53:28 |
Sebastian Huber |
riscv: Enable interrupts during dispatch after ISR
The code sequence …
5
|
|
|
@0fd8287
|
06/26/18 05:15:28 |
Sebastian Huber |
riscv: Add _CPU_Get_current_per_CPU_control()
Update #3433.
5
|
|
|
@2086948a
|
05/11/18 04:54:59 |
Sebastian Huber |
riscv: Add dummy SMP support
Update #3433.
5
|
|
|
@2afb22b
|
12/23/17 07:18:56 |
Chris Johns |
Remove make preinstall
A speciality of the RTEMS build system was the …
5
|