source: rtems/cpukit/score/cpu/riscv/include/rtems/score/cpu.h

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Diff Rev Age Author Log Message
(edit) @8db3f0e   07/19/18 10:11:19 Sebastian Huber riscv: Rework exception handling Remove … 5
(edit) @5694b0c   07/19/18 08:15:53 Sebastian Huber riscv: New CPU_Exception_frame Use the CPU_Interrupt_frame for the … 5
(edit) @d779a1e2   07/19/18 07:35:54 Sebastian Huber riscv: Add exception codes Update #3433. 5
(edit) @42f2fdfd   07/20/18 05:56:43 Sebastian Huber score: Move context validation declarations The context validation … 5
(edit) @248ca7a   07/20/18 07:10:29 Sebastian Huber score: Remove obsolete CPU port defines 5
(edit) @dd32e2b2   07/06/18 06:12:40 Sebastian Huber riscv: Implement CPU counter Update #3433. 5
(edit) @e755782   07/03/18 07:54:47 Sebastian Huber riscv: Clear reservations See also RISC-V User-Level ISA V2.3, … 5
(edit) @52352387   06/28/18 07:32:26 Sebastian Huber riscv: Add floating-point support Update #3433. 5
(edit) @afb60eb   06/27/18 12:46:06 Sebastian Huber riscv: Remove dead code Update #3433. 5
(edit) @e43994d   06/27/18 08:05:50 Sebastian Huber riscv: Optimize context switch and interrupts Save/restore … 5
(edit) @a8188730   06/27/18 07:43:39 Sebastian Huber riscv: Fix _CPU_Context_Initialize() prototype Update #3433. 5
(edit) @40f81ce6   06/27/18 10:18:09 Sebastian Huber riscv: Implement _CPU_Context_validate() Update #3433. 5
(edit) @71af1a4   06/27/18 10:17:21 Sebastian Huber riscv: Make some CPU port defines visible to asm Move SREG and LREG … 5
(edit) @8f035cb   06/27/18 06:57:08 Sebastian Huber riscv: Implement _CPU_Context_volatile_clobber() Update #3433. 5
(edit) @b706b4a   06/27/18 06:54:13 Sebastian Huber riscv: Remove mstatus from thread context The mstatus register … 5
(edit) @9510742   06/27/18 06:35:13 Sebastian Huber riscv: Fix CPU_STACK_ALIGNMENT According to the RISC-V psABI … 5
(edit) @98f051e   06/27/18 06:08:10 Sebastian Huber riscv: Remove RISCV_GCC_RED_ZONE_SIZE The current ABI says that there … 5
(edit) @9704d86f   06/26/18 06:53:28 Sebastian Huber riscv: Enable interrupts during dispatch after ISR The code sequence … 5
(edit) @3be4478f   06/26/18 05:13:28 Sebastian Huber riscv: Avoid namespace pollution Remove <rtems/score/riscv-utility.h> … 5
(edit) @bc3bdf2   06/28/18 12:59:38 Sebastian Huber riscv: Optimize and fix interrupt disable/enable Use the atomic read … 5
(edit) @2086948a   05/11/18 04:54:59 Sebastian Huber riscv: Add dummy SMP support Update #3433. 5
(edit) @7c3b0df1   06/22/18 11:30:49 Sebastian Huber riscv: Implement ISR set/get level Fix prototypes. Update #3433. 5
(edit) @511dc4b   06/19/18 07:09:51 Sebastian Huber Rework initialization and interrupt stack support Statically … 5
(edit) @c8df844   06/19/18 12:59:51 Sebastian Huber score: Add CPU_INTERRUPT_STACK_ALIGNMENT Add CPU port define for the … 5
(edit) @65f868c   05/23/18 12:17:25 Sebastian Huber Add _CPU_Counter_frequency() Add rtems_counter_frequency() API … 5
(edit) @f35c3be9   04/16/18 05:34:18 Sebastian Huber Remove register keyword from public header files The following code … 5
(edit) @5b88ec5   03/08/18 23:23:21 joel riscv/include/rtems/score/types.h: Eliminate this file Updates #3327. 5
(add) @2afb22b   12/23/17 07:18:56 Chris Johns Remove make preinstall A speciality of the RTEMS build system was the … 5
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