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rtems
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c
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lib
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libbsp
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arm
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shared
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arm-l2c-310
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Diff
Rev
Age
Author
Log Message
(edit)
@55741886
11/19/14 13:19:13
Sebastian Huber
bsps/arm: L2C 310 exclusive config is fatal
4.11
5
(edit)
@d53de34
11/19/14 13:08:44
Sebastian Huber
bsps/arm: L2C 310 use l2c_310_* prefix throughout
4.11
5
(edit)
@861d315
11/19/14 13:05:36
Sebastian Huber
bsps/arm: L2C 310 use L2C_310_* prefix throughout
4.11
5
(edit)
@f2fed0c1
11/19/14 11:24:07
Sebastian Huber
bsps/arm: L2C 310 add compile time checks Simplify initialization. …
4.11
5
(edit)
@13f1462f
11/19/14 11:07:04
Sebastian Huber
bsps/arm: L2C 310 delete invalid link
4.11
5
(edit)
@a9d6c20
11/19/14 11:23:02
Sebastian Huber
bsps/arm: L2C 310 simplify and remove white space
4.11
5
(edit)
@957c075
11/19/14 10:51:33
Sebastian Huber
bsps/arm: L2C 310 rename BSP_ARM_L2CC_BASE Rename BSP_ARM_L2CC_BASE …
4.11
5
(edit)
@12ab8d6
09/10/14 09:15:44
Sebastian Huber
bsps/arm: Fix get cache size
4.11
5
(edit)
@4768ae0f
09/10/14 09:10:04
Sebastian Huber
bsps/arm: Fix invalidate instruction cache Do not invalidate the …
4.11
5
(edit)
@40599e7e
06/05/14 08:01:42
Sebastian Huber
bsps/arm: Change L2 cache initialization Do not touch the L1 caches …
4.11
5
(edit)
@d98eea0
04/17/14 09:27:23
ralf.kirchner
bsp/arm: Cleanup L2 cache handling
4.11
5
(edit)
@127634c
04/17/14 09:22:53
ralf.kirchner
bsp/arm: Correct L2 cache enable method
4.11
5
(edit)
@62fa1ea
04/17/14 09:19:48
ralf.kirchner
bsp/arm: Add cache size methods Add new methods which deliver the …
4.11
5
(edit)
@1c62f74d
04/17/14 09:11:58
ralf.kirchner
bsp/arm: Add L2 cache locking This level 2 cache is a shared data and …
4.11
5
(edit)
@bebcfa57
04/17/14 09:03:50
ralf.kirchner
bsp/arm: Remove unused cache store methods
4.11
5
(edit)
@db5a84d
04/17/14 08:59:47
ralf.kirchner
bsp/arm: Correct cache misalignment handling Correct misalignment …
4.11
5
(edit)
@92e2757
04/17/14 08:37:10
ralf.kirchner
bsp/arm: Correct L2 cache flushing Correct misalignment handling and …
4.11
5
(edit)
@cbd9e63
04/17/14 08:30:54
ralf.kirchner
bsp/arm: Remove arm erratum 764369 from L2 cache Arm erratum 764369 …
4.11
5
(add)
@9fcd1b35
02/17/14 09:22:16
ralf.kirchner
bsp/arm: Add handling for level 2 L2C-310 cache controller …
4.11
5
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