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@26853a06
|
03/15/23 13:41:53 |
alan.cudmore |
bsps/riscv: add riscv/kendrytek210 BSP variant source changes
This …
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@ca1c4e70
|
03/15/23 13:39:20 |
alan.cudmore |
bsps/riscv: add device tree source and device tree blob header for …
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@11cc51e
|
03/16/23 08:00:43 |
Sebastian Huber |
bsps/riscv: Use per-CPU mtimecmp in clock driver
Use the mtimecmp …
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@cbddf5de
|
03/15/23 13:31:20 |
Sebastian Huber |
bsps/riscv: Fix riscv_get_hart_index_by_phandle()
Take a non-zero …
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@e5233057
|
03/16/23 07:31:08 |
Sebastian Huber |
bsps/riscv: Make SMP start more robust
In SMP configurations, check …
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@bb465c8
|
02/14/23 15:48:07 |
Sebastian Huber |
doxygen: Add Doxygen files to a group
Update #3707.
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@6136e28b
|
01/23/23 14:26:10 |
Sebastian Huber |
clockdrv: Add clock driver implementation group
Use standard wording …
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@10ee41a8
|
01/23/23 13:56:31 |
Sebastian Huber |
tm27: Avoid function pointer casts
Add TM27_USE_VECTOR_HANDLER to …
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@d46366a
|
01/11/23 07:27:40 |
Sebastian Huber |
riscv: Resurrect RISCV_ENABLE_HTIF_SUPPORT
Low-end configurations may …
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@88b80a5f
|
12/18/22 15:07:16 |
hesham.almatary |
RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORT
…
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@71d1acd
|
12/01/22 09:49:38 |
Sebastian Huber |
bsps/irq: Rename handler in dispatch table
The name handler table was …
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@d9c7db5
|
11/23/22 06:53:13 |
Sebastian Huber |
bsps/riscv: Simplify PLIC support
In uniprocessor configurations …
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@d448aa4
|
11/23/22 06:49:53 |
Sebastian Huber |
bsps/riscv: Fix PLIC enable register count
|
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|
@733d9b7
|
11/23/22 06:46:06 |
Sebastian Huber |
bsps/riscv: Add riscv_plic_cpu_0_init()
Move boot processor …
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@5756a6a
|
11/23/22 06:27:48 |
Sebastian Huber |
bsps/riscv: Fix bsp_fdt_map_intr()
The interrupt numbers in the …
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@18a181c2
|
11/14/22 10:00:14 |
cederman |
bsps/riscv: Change license to BSD-2 for files with Gaisler copyright
…
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@77c8d822
|
11/11/22 12:58:24 |
Sebastian Huber |
bsps/riscv: Fix software interrupt dispatching
In SMP configurations, …
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@908ffc7
|
11/11/22 15:35:15 |
Sebastian Huber |
bsps/noel: Fix interrupt support
|
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|
@bfdfc979
|
11/10/22 14:15:46 |
Sebastian Huber |
bsps/riscv: Fix PLIC enable register count
Each PLIC enable register …
|
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@e4210d5a
|
11/10/22 07:53:48 |
Sebastian Huber |
bsps/riscv: Skip init on not configured processors
|
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|
@3e5ccdd
|
11/10/22 07:40:54 |
Sebastian Huber |
bsps/riscv: Simplify riscv_plic_init()
|
|
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|
@d2bac3d7
|
11/10/22 07:21:47 |
Sebastian Huber |
bsps/riscv: Simplify riscv_clint_init()
|
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|
@ccf09a6e
|
11/09/22 13:45:45 |
Sebastian Huber |
bsps/riscv: Add tm27 support
|
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|
@ba53a17
|
11/09/22 13:46:44 |
Sebastian Huber |
bsps/riscv: Always dispatch software interrupts
This helps to run the …
|
|
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|
@47d156d7
|
11/09/22 15:08:08 |
Sebastian Huber |
bsps/riscv: bsp_interrupt_get/set_affinity()
Provide …
|
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|
@1bf1c77
|
11/09/22 09:18:29 |
Sebastian Huber |
bsps/riscv: bsp_interrupt_raise_on()
Implement …
|
|
|
|
@8a51ecc7
|
11/09/22 09:17:53 |
Sebastian Huber |
bsps/riscv: bsp_interrupt_is_pending()
Implement this function.
|
|
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|
@d156d7b
|
11/09/22 07:33:57 |
Sebastian Huber |
bsps/riscv: bsp_interrupt_get_attributes()
Implement this function.
|
|
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|
@a52fc42
|
11/09/22 07:20:52 |
Sebastian Huber |
bsps/riscv: Improve bsp_interrupt_vector_disable()
Add support for …
|
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|
@e19d490f
|
11/09/22 07:19:12 |
Sebastian Huber |
bsps/riscv: Improve bsp_interrupt_vector_enable()
Add support for …
|
|
|
|
@16c352de
|
11/08/22 14:06:49 |
Sebastian Huber |
bsps/riscv: bsp_interrupt_vector_is_enabled()
Implement this function.
|
|
|
|
@9c80a88
|
11/09/22 13:46:11 |
Sebastian Huber |
bsps/riscv: bsp_interrupt_is_valid_vector()
Implement this function.
|
|
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|
@b4ffaa7c
|
11/04/22 12:47:45 |
Sebastian Huber |
bsps/riscv: Use start data for object
Maybe this helps to ensure that …
|
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|
@89ba2a98
|
10/27/22 12:40:26 |
Sebastian Huber |
bsps/riscv: Workaround for sporadic linker issues
Disable the linker …
|
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|
|
@1d2fab8
|
09/29/22 16:11:59 |
alan.cudmore |
bsps: Improve riscv console FDT parsing
This fixes a problem with …
|
|
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|
@e9a69c5
|
10/14/22 08:52:00 |
Sebastian Huber |
riscv: Move functions to avoid build issues
The …
|
|
|
|
@6b0d3c9
|
09/19/22 13:00:26 |
padmarao.begari |
bsps/riscv: Add Microchip PolarFire? SoC BSP variant
The Microchip …
|
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|
@9cdc008
|
09/19/22 13:00:24 |
padmarao.begari |
bsps/riscv: Add device tree blob
Add the basic Microchip PolarFire? …
|
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|
@88f4d44f
|
09/18/22 19:22:29 |
alan.cudmore |
bsps/riscv/riscv: Fix fe310_uart_read
Note: Resending after learning …
|
|
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|
@9ec9be83
|
02/01/21 14:18:21 |
maberg |
bsp/riscv: Add NOEL-V BSP
Added support for Cobham Gaisler NOEL-V …
|
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|
@ca07efd5
|
08/17/22 07:19:26 |
cederman |
bsp/riscv: Work area size based on /memory node in fdt
Uses the first …
|
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|
@faaffbd9
|
02/25/22 16:45:06 |
Sebastian Huber |
riscv: Use zicsr architecture extension
This is required for ISA 2.0 …
|
|
|
|
@4b09a4c7
|
02/25/22 18:43:11 |
Sebastian Huber |
bsps/riscv: Add missing include
|
|
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|
@dd70c81
|
11/25/21 01:43:10 |
joel |
bsp_specs: Delete last remnants of these.
Updates #3937.
|
|
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|
@db8f598
|
04/26/21 12:00:41 |
Sebastian Huber |
build: Remove old build system
Close #3250.
Close #4081.
|
|
|
|
@8b65b574
|
07/28/21 12:41:32 |
Sebastian Huber |
score: Canonicalize _CPU_Fatal_halt()
Move _CPU_Fatal_halt() …
|
|
|
|
@c7b4eca7
|
07/27/21 07:58:43 |
Sebastian Huber |
bsps/irq: bsp_interrupt_facility_initialize()
Do not return a status …
|
|
|
|
@85a3785
|
07/06/21 17:00:20 |
Sebastian Huber |
bsps/irq: bsp_interrupt_set_affinity()
Return a status code for …
|
|
|
|
@23ec04c
|
07/06/21 16:39:57 |
Sebastian Huber |
bsps/irq: bsp_interrupt_get_affinity()
Return a status code for …
|
|
|
|
@32f5a195
|
06/29/21 12:06:03 |
Sebastian Huber |
bsps/irq: bsp_interrupt_vector_disable()
Return a status code for …
|
|
|
|
@bc86a5fa
|
06/29/21 12:01:17 |
Sebastian Huber |
bsps/irq: bsp_interrupt_vector_enable()
Return a status code for …
|
|
|
|
@deb5afb
|
07/05/21 11:28:02 |
Sebastian Huber |
bsps/irq: Add rtems_interrupt_is_pending()
Add a default …
|
|
|
|
@eebecd0
|
06/28/21 07:36:29 |
Sebastian Huber |
bsps/irq: Add rtems_interrupt_get_attributes()
Add a default …
|
|
|
|
@9832652c
|
06/28/21 06:44:49 |
Sebastian Huber |
bsps/irq: Add rtems_interrupt_raise()
Add rtems_interrupt_raise_on() …
|
|
|
|
@781213f9
|
06/28/21 06:20:53 |
Sebastian Huber |
bsps/irq: Add rtems_interrupt_vector_is_enabled()
Add a default …
|
|
|
|
@94cf67c
|
06/19/21 10:48:27 |
Sebastian Huber |
bsps/irq: Remove BSP_INTERRUPT_VECTOR_MAX
This define is no longer …
|
|
|
|
@cd5573c
|
06/19/21 10:40:57 |
Sebastian Huber |
bsps/irq: Add BSP_INTERRUPT_VECTOR_COUNT
Assert …
|
|
|
|
@af73b7b6
|
06/18/21 05:37:18 |
Sebastian Huber |
bsps/irq: Remove BSP_INTERRUPT_VECTOR_MIN
Remove …
|
|
|
|
@af69a869
|
06/10/21 13:01:49 |
Sebastian Huber |
grlib: Add apbuart_outbyte_wait()
|
|
|
|
@85febe7b
|
06/10/21 12:51:38 |
Sebastian Huber |
grlib: Remove NL -> CR in apbuart_outbyte_polled()
This is already …
|
|
|
|
@2c07f24
|
06/10/21 11:04:13 |
Sebastian Huber |
grlib: Add ambapp_plb()
Replace the global variable ambapp_plb with a …
|
|
|
|
@e10dec0
|
04/30/21 13:47:10 |
Sebastian Huber |
bsps: Support RTEMS_NOINIT in linkcmds
Update #3866.
|
|
|
|
@c90fa83
|
02/25/21 02:09:56 |
vijay |
bsps: Remove networking drivers
Update #3850
|
|
|
|
@1343fb5f
|
03/19/21 11:12:09 |
jan.sommer |
bsps/riscv: Add per cpu clock interrupt
- Fixes failure of test smpclock01
|
|
|
|
@570992dc
|
02/09/21 07:17:21 |
Sebastian Huber |
bsp/riscv: Re-license to BSD-2-Clause
Change license to BSD-2-Clause …
|
|
|
|
@b361eabd
|
01/28/21 05:28:33 |
Sebastian Huber |
bsps: Replace bsp_specs with an empty file
This fixes an issue with …
|
|
|
|
@9eb9813
|
01/26/21 14:29:00 |
Sebastian Huber |
bsps: Add missing DWARF 5 sections
Sort alphabetically.
|
|
|
|
@33c12d5
|
01/25/21 10:19:21 |
Sebastian Huber |
bsps: Support DWARF 5 sections
GCC 11 uses DWARF 5 by default.
|
|
|
|
@b4c29b5
|
10/24/20 14:43:49 |
Jiri Gaisler |
Add networking support for griscv bsp
* Only GRETH device supported …
|
|
|
|
@e1a0e0c3
|
10/08/20 05:50:10 |
Sebastian Huber |
grlib: Add and use irqmp_has_timestamp()
Replace …
|
|
|
|
@e8450a6c
|
09/22/20 15:38:12 |
Sebastian Huber |
bsps/riscv: Add bsp_fdt_map_intr()
This function is required by libbsd.
|
|
|
|
@4897a82d
|
09/15/20 07:07:29 |
Hesham.Almatary |
riscv: Make sifive_test finisher 4 bytes
QEMU is now stricter with …
|
|
|
|
@2786b0a
|
09/13/20 14:13:14 |
Sebastian Huber |
bsps/riscv: Use far jump to boot_card()
Use a far jump to avoid …
|
|
|
|
@764ea578
|
09/06/20 21:07:29 |
Hesham.Almatary |
htif_console_handler is defined in htif.c
closes #4069.
|
|
|
|
@d556af36
|
08/31/20 12:12:14 |
Sebastian Huber |
bsps: Always install IPI in SMP configs
The inter-processor interrupt …
|
|
|
|
@d35722e6
|
04/08/20 09:52:45 |
Sebastian Huber |
bsps/riscv: Fix multiple definition
5
|
|
|
|
@0161b93d
|
03/03/20 18:23:53 |
Sebastian Huber |
imfs: Replace devfs with an IMFS specialization
Add a simplified path …
5
|
|
|
|
@c344e58
|
02/02/20 10:00:54 |
Sebastian Huber |
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5 …
5
|
|
|
|
@ffa1153
|
12/14/19 20:36:09 |
Sebastian Huber |
bsps: Add RamEnd? to linker command files
Update #3838.
5
|
|
|
|
@f4fda72
|
11/29/19 18:01:00 |
Sebastian Huber |
Regenerate headers.am
5
|
|
|
|
@ae554670
|
11/14/19 10:20:41 |
Sebastian Huber |
bsp/riscv: Fix format and warnings
Update #3785.
5
|
|
|
|
@e9ae7436
|
11/14/19 10:15:19 |
Sebastian Huber |
bsp/riscv: Fix use of uninitialized integer
5
|
|
|
|
@df9426f
|
11/14/19 10:08:28 |
Sebastian Huber |
bsp/riscv: riscv_get_core_frequency()
Always provide this function. …
5
|
|
|
|
@044687d3
|
03/31/19 12:49:19 |
Hesham.Almatary |
bsps/riscv: UART - Read reg-shift from DTB to properly set/get registers
5
|
|
|
|
@94481ce
|
10/24/19 12:05:07 |
Hesham.Almatary |
riscv: Add new BSP cfg variants to be built with llvm/clang
5
|
|
|
|
@ce5988e
|
10/23/19 11:52:54 |
Hesham.Almatary |
riscv: Add new offending input sections to the linker script
5
|
|
|
|
@7f0c41c7
|
10/23/19 11:50:55 |
Hesham.Almatary |
riscv: Add NOLOAD directive to the .work section
ld.lld defaults …
5
|
|
|
|
@f462bcb
|
10/23/19 11:43:17 |
Hesham.Almatary |
riscv: Address differences in the linkerscript between GNU LD and …
5
|
|
|
|
@ca82ded7
|
10/23/19 11:37:12 |
Hesham.Almatary |
riscv: Generate linkcmds.base from the shared linkcmds.base.in
This …
5
|
|
|
|
@a7f5e42c
|
10/22/19 10:20:05 |
pragnesh.patel |
riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom …
5
|
|
|
|
@ad87de4
|
04/11/19 06:54:29 |
Sebastian Huber |
score: Rename _SMP_Get_processor_count()
Rename …
5
|
|
|
|
@f9219db
|
04/05/19 06:16:05 |
Sebastian Huber |
rtems: Add rtems_scheduler_get_processor_maximum()
Add …
5
|
|
|
|
@828276b
|
03/05/19 06:58:18 |
Sebastian Huber |
bsps: Adjust shared Doxygen groups
Update #3706.
5
|
|
|
|
@c991eeec
|
03/04/19 14:32:15 |
Sebastian Huber |
bsps: Adjust bsp.h Doxygen groups
Update #3706.
5
|
|
|
|
@212663be
|
02/26/19 14:44:50 |
Sebastian Huber |
bsps: Adjust architecture Doxygen groups
- Use CamelCase as it is …
5
|
|
|
|
@568490a
|
02/08/19 11:40:45 |
Jiri Gaisler |
griscv: add additional cpu configurations
* Also switch default …
5
|
|
|
|
@d3d4e77
|
01/18/19 11:37:55 |
Jiri Gaisler |
riscv: add griscv bsp
Update #3678.
5
|
|
|
|
@9aee88a
|
01/08/19 13:43:02 |
Sebastian Huber |
bsp/riscv: Clear boot command line
5
|
|
|
|
@ff081aee
|
11/06/18 15:58:02 |
Sebastian Huber |
score: Rename interrupt stack symbols
Rename
* …
5
|
|
|
|
@9cda6f29
|
09/17/18 12:12:07 |
Hesham.Almatary |
riscv: Allow platforms with no PLIC to proceed
Spike simulator and …
5
|
|
|
|
![[RTEMS Logo]](/images/logo.png){kind=logo}
