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@e8450a6c
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09/22/20 15:38:12 |
Sebastian Huber |
bsps/riscv: Add bsp_fdt_map_intr()
This function is required by libbsd.
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@4897a82d
|
09/15/20 07:07:29 |
Hesham.Almatary |
riscv: Make sifive_test finisher 4 bytes
QEMU is now stricter with …
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@764ea578
|
09/06/20 21:07:29 |
Hesham.Almatary |
htif_console_handler is defined in htif.c
closes #4069.
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@c344e58
|
02/02/20 10:00:54 |
Sebastian Huber |
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5
Use RTEMS_SYSINIT_ORDER_LAST_BUT_5 …
5
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@f4fda72
|
11/29/19 18:01:00 |
Sebastian Huber |
Regenerate headers.am
5
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@ae554670
|
11/14/19 10:20:41 |
Sebastian Huber |
bsp/riscv: Fix format and warnings
Update #3785.
5
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@e9ae7436
|
11/14/19 10:15:19 |
Sebastian Huber |
bsp/riscv: Fix use of uninitialized integer
5
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@df9426f
|
11/14/19 10:08:28 |
Sebastian Huber |
bsp/riscv: riscv_get_core_frequency()
Always provide this function. …
5
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@044687d3
|
03/31/19 12:49:19 |
Hesham.Almatary |
bsps/riscv: UART - Read reg-shift from DTB to properly set/get registers
5
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@94481ce
|
10/24/19 12:05:07 |
Hesham.Almatary |
riscv: Add new BSP cfg variants to be built with llvm/clang
5
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@a7f5e42c
|
10/22/19 10:20:05 |
pragnesh.patel |
riscv: add freedom E310 Arty A7 bsp
Added support for Sifive Freedom …
5
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@ad87de4
|
04/11/19 06:54:29 |
Sebastian Huber |
score: Rename _SMP_Get_processor_count()
Rename …
5
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@c991eeec
|
03/04/19 14:32:15 |
Sebastian Huber |
bsps: Adjust bsp.h Doxygen groups
Update #3706.
5
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@d3d4e77
|
01/18/19 11:37:55 |
Jiri Gaisler |
riscv: add griscv bsp
Update #3678.
5
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@9aee88a
|
01/08/19 13:43:02 |
Sebastian Huber |
bsp/riscv: Clear boot command line
5
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@ff081aee
|
11/06/18 15:58:02 |
Sebastian Huber |
score: Rename interrupt stack symbols
Rename
* …
5
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@9cda6f29
|
09/17/18 12:12:07 |
Hesham.Almatary |
riscv: Allow platforms with no PLIC to proceed
Spike simulator and …
5
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@141d502
|
08/02/18 11:23:26 |
Sebastian Huber |
bsp/riscv: Add missing BSP variant
Update #3433.
5
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@4c740de
|
08/02/18 12:13:25 |
Sebastian Huber |
bsp/riscv: Fix build with RTEMS_SMP undefined
Update #3433.
5
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@3d11c1e
|
08/01/18 08:06:37 |
Sebastian Huber |
bsp/riscv: Fix a synchronization issue for PLIC
Update #3433.
5
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@dee2ebb
|
08/01/18 09:15:55 |
Sebastian Huber |
bsp/riscv: Remove unused variable
Update #3433.
5
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@56b0387
|
08/01/18 06:13:39 |
Sebastian Huber |
bsp/riscv: Add NS16750 support to console driver
Update #3433.
5
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@529154b
|
07/31/18 07:15:00 |
Sebastian Huber |
bsp/riscv: Initialize FPU depending on ISA
Initialize fcsr to zero …
5
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@48cbd63
|
07/31/18 05:19:33 |
Sebastian Huber |
bsp/riscv: Fix clock driver
Do not assume that mtime is zero at boot …
5
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@44c2d393
|
07/27/18 13:04:38 |
Sebastian Huber |
bsp/riscv: Fix inter-processor interrupts
The previous version worked …
5
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@cfc9573
|
07/27/18 12:47:17 |
Sebastian Huber |
riscv: Rework CPU counter support
Update #3433.
5
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@581a0f88
|
07/24/18 12:47:05 |
Sebastian Huber |
bsp/riscv: Use interrupt driven NS16550 driver
Update #3433.
5
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@adede135
|
07/24/18 11:27:54 |
Sebastian Huber |
bsp/riscv: Add PLIC support
Update #3433.
5
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@bd560386
|
07/23/18 11:50:02 |
Sebastian Huber |
bsp/riscv: Add simple SMP support to clock driver
This is a hack. …
5
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@6552ba8
|
07/24/18 08:10:12 |
Sebastian Huber |
bsp/riscv: Use CPU counter btimer
Update #3433.
5
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@447fd89
|
07/20/18 11:11:04 |
Sebastian Huber |
bsp/riscv: Add basic SMP startup
Update #3433.
5
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@6b9ef09
|
07/20/18 08:57:59 |
Sebastian Huber |
riscv: Add CLINT and PLIC support
The CLINT and PLIC need some …
5
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@dda6e06
|
07/19/18 12:45:47 |
Sebastian Huber |
bsp/riscv: Add reset via for SiFive? Test Finisher
Update #3433.
5
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@3a263a9b
|
07/19/18 12:38:44 |
Sebastian Huber |
bsp/riscv: Add and use riscv_fdt_get_address()
Update #3433.
5
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@7fe4855
|
07/19/18 11:58:12 |
Sebastian Huber |
bsp/riscv: Fix HTIF warnings
Update #3433.
5
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@8db3f0e
|
07/19/18 10:11:19 |
Sebastian Huber |
riscv: Rework exception handling
Remove …
5
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@1a19239
|
07/06/18 09:20:31 |
Sebastian Huber |
bsp/riscv: Add console support for NS16550 devices
Update #3433.
5
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@31f90a2
|
07/06/18 11:52:22 |
Sebastian Huber |
bsp/riscv: Simplify printk() support
This is a prepartion to add …
5
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@bca36d9
|
07/06/18 09:07:20 |
Sebastian Huber |
riscv: Add LADDR assembler define
An address must be loaded to a …
5
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@dd32e2b2
|
07/06/18 06:12:40 |
Sebastian Huber |
riscv: Implement CPU counter
Update #3433.
5
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@d3dff40
|
07/04/18 14:15:22 |
Sebastian Huber |
bsps: Update headers.am
5
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@0fd8287
|
06/26/18 05:15:28 |
Sebastian Huber |
riscv: Add _CPU_Get_current_per_CPU_control()
Update #3433.
5
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@3be4478f
|
06/26/18 05:13:28 |
Sebastian Huber |
riscv: Avoid namespace pollution
Remove <rtems/score/riscv-utility.h> …
5
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@ff7b104
|
06/27/18 05:47:33 |
Sebastian Huber |
bsp/riscv: Remove bsp_interrupt_handler_default()
It duplicated the …
5
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@cdfed94f
|
06/25/18 09:12:24 |
Sebastian Huber |
bsp/riscv: Rework clock driver
Use device tree provided timebase …
5
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@1232cd46
|
06/25/18 06:44:16 |
Sebastian Huber |
bsp/riscv: Add device tree support for console
Update #3433.
5
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@c558cc4
|
06/28/18 11:04:58 |
Sebastian Huber |
bsp/riscv: Fix vector table for lp64
Update #3433.
5
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@5f5c450
|
06/22/18 11:58:11 |
Sebastian Huber |
bsp/riscv: Add SMP startup synchronization
Update #3433.
5
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@fe2cd01b
|
06/22/18 06:01:48 |
Sebastian Huber |
bsp/riscv: Add device tree support
Update #3433.
5
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@2086948a
|
05/11/18 04:54:59 |
Sebastian Huber |
riscv: Add dummy SMP support
Update #3433.
5
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@9b2ef07f
|
06/22/18 11:30:21 |
Sebastian Huber |
bsp/riscv: Load global pointer
Update #3433.
5
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@b0ee789
|
06/22/18 09:14:07 |
Sebastian Huber |
bsp/riscv: Use memset() to clear .bss
Update #3433.
5
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@52f4fb6
|
06/26/18 05:48:06 |
Sebastian Huber |
riscv: Format assembler files
Use tabs to match the GCC generated …
5
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@fef0a41
|
06/22/18 07:03:19 |
Sebastian Huber |
bsp/riscv: Do not clear integer registers at start
There is no need …
5
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@38024362
|
06/22/18 09:00:01 |
Sebastian Huber |
bsp/riscv: Fix some warnings
Update #3444.
5
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@16d905f
|
06/22/18 05:51:08 |
Sebastian Huber |
bsp/riscv: Add BSP options to define RAM region
Update #3433.
5
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@f3da074a
|
06/22/18 05:10:44 |
Sebastian Huber |
bsp/riscv: Add new BSP variants
The latest RISC-V tool chain …
5
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@6f5d88a
|
06/22/18 05:06:57 |
Sebastian Huber |
bsp/riscv_generic: Rename to "riscv"
Update #3433.
5
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