; /* @(#)register.ah	1.1 96/05/23 08:56:57, TEI */
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;		 naming of various registers    
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; /* $Id$ */

;* File information and includes.

	.file	"register.ah"
	.ident	"@(#)register.ah	1.1 96/05/23 08:56:57, TEI\n"

;* Register Stack pointer and frame pointer registers.

	.extern	Rrsp, Rfp

	.reg	regsp, 		%%Rrsp
	.reg	fp, 		%%Rfp


	.extern RTrapReg
	.extern Rtrapreg

	.reg	TrapReg, 	%%RTrapReg
	.reg	trapreg, 	%%Rtrapreg


;* Operating system Interrupt handler registers (gr64-gr67)

	.extern	ROSint0, ROSint1, ROSint2, ROSint3

	.reg	OSint0, 	%%ROSint0
	.reg	OSint1, 	%%ROSint1
	.reg	OSint2, 	%%ROSint2
	.reg	OSint3, 	%%ROSint3

	.reg	it0, 		%%ROSint0
	.reg	it1, 		%%ROSint1
	.reg	it2, 		%%ROSint2
	.reg	it3, 		%%ROSint3



;* Operating system temporary (or scratch) registers (gr68-gr79)

	.extern	ROStmp0, ROStmp1, ROStmp2, ROStmp3
	.extern	ROStmp4, ROStmp5, ROStmp6, ROStmp7
	.extern	ROStmp8, ROStmp9, ROStmp10, ROStmp11

	.reg	OStmp0, 	%%ROStmp0
	.reg	OStmp1, 	%%ROStmp1
	.reg	OStmp2, 	%%ROStmp2
	.reg	OStmp3, 	%%ROStmp3

	.reg	OStmp4, 	%%ROStmp4
	.reg	OStmp5, 	%%ROStmp5
	.reg	OStmp6, 	%%ROStmp6
	.reg	OStmp7, 	%%ROStmp7

	.reg	OStmp8, 	%%ROStmp8
	.reg	OStmp9, 	%%ROStmp9
	.reg	OStmp10, 	%%ROStmp10
	.reg	OStmp11, 	%%ROStmp11


	.reg	kt0, 		%%ROStmp0
	.reg	kt1, 		%%ROStmp1
	.reg	kt2, 		%%ROStmp2
	.reg	kt3, 		%%ROStmp3

	.reg	kt4, 		%%ROStmp4
	.reg	kt5, 		%%ROStmp5
	.reg	kt6, 		%%ROStmp6
	.reg	kt7, 		%%ROStmp7

	.reg	kt8, 		%%ROStmp8
	.reg	kt9, 		%%ROStmp9
	.reg	kt10, 		%%ROStmp10
	.reg	kt11, 		%%ROStmp11


	.reg	TempReg0,	%%ROSint0
	.reg	TempReg1, 	%%ROSint1
	.reg	TempReg2, 	%%ROSint2
	.reg	TempReg3, 	%%ROSint3

	.reg	TempReg4, 	%%ROStmp0
	.reg	TempReg5, 	%%ROStmp1
	.reg	TempReg6, 	%%ROStmp2
	.reg	TempReg7, 	%%ROStmp3

	.reg	TempReg8, 	%%ROStmp4
	.reg	TempReg9, 	%%ROStmp5
	.reg	TempReg10, 	%%ROStmp6
	.reg	TempReg11, 	%%ROStmp7

	.reg	TempReg12, 	%%ROStmp8
	.reg	TempReg13, 	%%ROStmp9
	.reg	TempReg14, 	%%ROStmp10
	.reg	TempReg15, 	%%ROStmp11


;* Assigned static registers

	.extern	RSpillAddrReg, RFillAddrReg, RSignalAddrReg
	.extern	Rpcb, Retc
	.extern	RTimerExt, RTimerUtil, RLEDReg, RERRReg
	.extern	Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb
	.extern	Retx, Rety, Retz


	.reg	SpillAddrReg, 	%%RSpillAddrReg
	.reg	FillAddrReg, 	%%RFillAddrReg
	.reg	SignalAddrReg, 	%%RSignalAddrReg
	.reg	pcb,		%%Rpcb

	.reg	etx,		%%Retx
	.reg	ety,		%%Rety
	.reg	etz,		%%Retz
	.reg	eta,		%%Reta

	.reg	etb,		%%Retb
	.reg	etc,		%%Retc
	.reg	TimerExt, 	%%RTimerExt
	.reg	TimerUtil, 	%%RTimerUtil

	.reg	LEDReg, 	%%RLEDReg
	.reg	ERRReg, 	%%RERRReg


	.reg	et0,		%%Ret0
	.reg	et1,		%%Ret1
	.reg	et2,		%%Ret2
	.reg	et3,		%%Ret3

	.reg	et4,		%%Ret4
	.reg	et5,		%%Ret5
	.reg	et6,		%%Ret6
	.reg	et7,		%%Ret7

;
	.equ	SCB1REG_NUM,	88	
	.reg	SCB1REG_PTR,	%%Ret0

; The floating point trap handlers need a few static registers

        .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3
        .extern Rheapptr, RHeapPtr, RArgvPtr

        .reg    FPStat0, 	%%RFPStat0
        .reg    FPStat1, 	%%RFPStat1
        .reg    FPStat2, 	%%RFPStat2
        .reg    FPStat3, 	%%RFPStat3

        .reg    heapptr, 	%%Rheapptr
        .reg    HeapPtr, 	%%RHeapPtr
        .reg    ArgvPtr, 	%%RArgvPtr

        .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg

        .reg    XLINXReg,	%%RXLINXReg
        .reg    VMBCReg,	%%RVMBCReg
        .reg    UARTReg,	%%RUARTReg
        .reg    ETHERReg,	%%RXLINXReg

;* Compiler and programmer registers. (gr96-gr127)

	.extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9
	.extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15

	.reg	v0, 		%%Rv0
	.reg	v1, 		%%Rv1
	.reg	v2, 		%%Rv2
	.reg	v3, 		%%Rv3

	.reg	v4, 		%%Rv4
	.reg	v5, 		%%Rv5
	.reg	v6, 		%%Rv6
	.reg	v7, 		%%Rv7

	.reg	v8, 		%%Rv8
	.reg	v9, 		%%Rv9
	.reg	v10, 		%%Rv10
	.reg	v11, 		%%Rv11

	.reg	v12, 		%%Rv12
	.reg	v13, 		%%Rv13
	.reg	v14, 		%%Rv14
	.reg	v15, 		%%Rv15

	.extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4

	.reg	tv0, 		%%Rtv0
	.reg	tv1, 		%%Rtv1
	.reg	tv2, 		%%Rtv2
	.reg	tv3, 		%%Rtv3
	.reg	tv4, 		%%Rtv4

; ****************************************************************************
;	For uatrap
; register definitions -- since this trap handler must allow for
; nested traps and interrupts such as TLB miss, protection violation,
; or Data Access Exception, and these trap handlers use the shared
; Temp registers, we must maintain our own that are safe over user-
; mode loads and stores.  The following must be assigned global
; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss,
; TLB protection violation, or data exception trap handlers.

;	.reg	cha_cpy, 	OStmp4		; copy of CHA
;	.reg	chd_cpy, 	OStmp5		; copy of CHD
;	.reg	chc_cpy, 	OStmp6		; copy of CHC
;	.reg	LTemp0, 	OStmp7		; local temp 0
;	.reg	LTemp1, 	OStmp8		; local temp 1

; ****************************************************************************