Avenger Control Electronics System
**********************************

General System
==============

Monitor and Control Avenger
---------------------------

The AFCC shall be the main computer that monitors and controls all AVENGER system functions.  [MNTMN 1-21.b, MNTMN 11-3]

Control Weapons
---------------

The AFCC shall be capable of tracking a single target, and controlling the missile and machine-gun systems.  [FUNCTIONAL]

Handle Tone Signals
-------------------

The AFCC shall receive a tone signal from the IEA and IFF system.  [MNTMN 11-3.a(3), MNTMN 11-3.b(1)] The AFCC shall generate a test tone.  [MNTMN 11-3.a(3), MNTMN 11-3.b(2)] The AFCC shall also amplify the tone signals (target acquisition tone and IFF tone) from the IEA and IFF system and apply them to the communications system via the gunner's control box to the CVC helmet.  [MNTMN 11-3.a(3), MNTMN 11-3.b(2)] The IFF audio tone shall be mixed with the missile acquisition tone and built-in-test tone inside the AFCC.  [MNTMN 11-3.a(3), MNTMN 12-5.b(3&4)].

Provide AVDAS
-------------

The AFCC shall provide system status information on the AVDAS serial test port.  [FUNCTIONAL]

Perform Initial Power-On Sequence
---------------------------------

During power-on, the AFCC shall perform the following:

  * initialize all software programmable peripherals,

  * set all A/D output values to zero,

  * safe the laser range finder by setting both first return and last return to a high state,

  * safe the machine-gun system,

  * set the turret drive to high speed mode,

  * set the following outputs inactive

      1. FLIR fire permit, missile active, RSO authorize, and uncage verify

      2. sight fire permit, missile active, RSO authorize, and uncage verify

      3. sight display active, and driven reticle

      4. power interlock

      5. FLIR field of view

      6. IFF challenge

      7. gunner palm grips and drift switch

      8. fire command

      9. uncage command

      10. BIT initiate command

      11. ATAS power on

      12. sequence command

      13. arm command

      14. activate command

      15. autotrack lock on command

      16. laser fire command,

  * set the following inputs to the indicated state

      1. uncage mode to AUTO

      2. helicopter mode to OFF

      3. track mode to MANUAL

      4. turret drive mode to STAB.

  * initialize the missile range tables in RAM from values in EPROM,

  * clear the north reference value and fire permit limits.  [FUNCTIONAL]

Perform Post-power-on Initialization -- Deleted
-----------------------------------------------

Requirement was deleted.

Update AVDAS Port
-----------------

The AFCC shall update the AVDAS port every 100ms.  [FUNCTIONAL]

Handle Minor Faults
-------------------

Detection of a minor fault shall cause an error message to be displayed on the CDT and the system fault light to be lit.

System Modes
============

General Mode
------------

Process System Mode Periodically -- Deleted
...........................................

Requirement was deleted.

Determine System Mode
.....................

The AFCC shall determine the system mode from the state of the system mode switch on the gunner's console and the remote mode indication from the remote terminal.  [FUNCTIONAL]

OFF Mode
........

If the system mode switch is in the OFF position, the system mode shall be OFF.  [FUNCTIONAL]

COMM Mode
.........

If the system mode switch is in the COMM position, the system mode shall be COMM.  [FUNCTIONAL]

SAFE Mode
.........

If the system mode switch is in the SAFE position, the system mode shall be SAFE.  [FUNCTIONAL]

RUN Mode
........

If the system mode switch is in the RUN position, the system mode shall be RUN.  [FUNCTIONAL]

ENGAGE Mode
...........

If the system mode switch is in the ENGAGE position, the system mode shall be ENGAGE or REMOTE.  [FUNCTIONAL]

Mode Fault
..........

If the system mode switch is not in a valid position, the system mode shall remain unchanged and the AFCC shall output 'MODE FAULT' to the CDT. [FUNCTIONAL]

ENGAGE Mode Processing
......................

When the system is in the ENGAGE mode, the AFCC shall:

  * perform auto slew processing,

  * perform lead angle processing,

  * perform autotrack processing,

  * output rate commands to the turret drive system,

  * control the firing of the weapons systems.  [FUNCTIONAL]

Mode Transition
---------------

The AFCC can operate in one of the following modes:  OFF, COMM, SAFE, RUN, or ENGAGE.  The mode transitions are depicted in Figure 3-1.

Process Transition to OFF Mode
..............................

When the AFCC detects a valid transition to the OFF mode, the following actions shall be performed:

  * update the elapsed time counter for the last mode the system was in,

  * output 'OFF MODE' to the CDT,

  * safe the laser by setting the last and first return to a high state,

  * disable the turret drive system,

  * disable the missile system,

  * disable the machine-gun system,

  * deactivate the sight and reticle,

  * update the EEPROM with the current elapsed time and count values,

  * disable continuous BIT,

  * insure that the machine-gun cool down has completed before clearing the power hold circuit.  [FUNCTIONAL]

Process Transition to COMM Mode
...............................

When the AFCC detects a valid transition to the COMM mode, the following actions shall be performed:

  * update the elapsed time counter for the last mode the system was in,

  * output `COMM MODE' to the CDT,

  * safe the laser by setting the last and first return to a high state,

  * disable the turret drive system,

  * disable the missile system,

  * disable the machine-gun system,

  * deactivate the sight and reticle,

  * reset the power hold circuit to insure power if the system is put in the OFF mode,

  * enable current monitoring.  [OPMAN 2-27.b(2), FUNCTIONAL]

Process Transition to SAFE Mode
...............................

When the AFCC detects a valid transition to the SAFE mode, the following actions shall be performed:

  * update the elapsed time counter for the last mode the system was in,

  * output `SAFE MODE' to the CDT,

  * safe the laser by setting the last and first return to a high state,

  * disable the turret drive system,

  * disable the missile system,

  * disable the machine-gun system,

  * deactivate the sight and reticle,

  * reset the power hold circuit to insure power if the system is put in the OFF mode,

  * enable current monitoring.  [FUNCTIONAL]

Process Transition to RUN Mode
..............................

When the AFCC detects a valid transition to the RUN mode, the following actions shall be performed:

  * update the elapsed time counter for the last mode the system was in,

  * output `RUN MODE' to the CDT,

  * safe the laser by setting the last and first return to a high state,

  * enable the turret drive system,

  * disable the missile system,

  * disable the machine-gun system,

  * deactivate the sight and reticle,

  * reset the power hold circuit to insure power if the system is put in the OFF mode,

  * enable current monitoring.  [FUNCTIONAL]

Process Transition to ENGAGE Mode
.................................

When the AFCC detects a valid transition to the ENGAGE mode, the following actions shall be performed:

  * update the elapsed time counter for the last mode the system was in,

  * output `ENGAGE MODE' to the CDT,

  * enable the turret drive system,

  * enable the missile system power,

  * reset the power hold circuit to insure power if the system is put in the OFF mode,

  * enable current monitoring.  [FUNCTIONAL]

System BIT
==========

Boot BIT
--------

Perform ROM Checksum
....................

During initialization of the AFCC, the AFCC shall checksum the code image stored in ROM to insure that it is correct.  If the checksum does not match the code image, the system shall halt.

Boot Test AFCC Boards
.....................

During initialization of the AFCC, all boards shall be tested to determine their functional state.  If all tests performed on a board pass, the board shall have a functional state of passed.  If any test performed on a board fails, the board shall have a functional state of failed.

Boot Test CPU Board
...................

During initialization of the AFCC, the AFCC shall test the following CPU board components by invoking all non-destructive card-level diagnostic tests provided by the CPU board vendor.  If any CPU board component fails diagnostic testing, a fatal error shall occur.

Boot Test AFCC Controller Board DAC's
.....................................

During initialization of the AFCC, the AFCC shall utilize the DAC test capability of the AFCC Controller board to verify that the DAC components of the AFCC Controller board are set to their initial values.  If any DAC component is not properly set, a fatal error shall occur.

Boot Test Interface Board Discrete Inputs
.........................................

During initialization of the AFCC, the AFCC shall utilize the discrete input loopback capability of the AFCC Interface board to test that the discrete input components of the AFCC Interface board are working properly.  If any discrete input component does not function properly, a fatal error shall occur.

Boot Test AFCC Controller Board Relay and Discrete Outputs
..........................................................

During initialization of the AFCC, the AFCC shall utilize the relay and discrete output test capability of the AFCC Controller board to verify that the relay and discrete output components of the AFCC Controller board are set to their initial values.  If any relay or discrete output component is not properly set, a fatal error shall occur.

Boot Check Voltages
...................

During initialization of the AFCC, the +5 volt, +15 volt, -15 volt, and +28 volt power supplies shall be checked to insure that they are within tolerance.  If any of the power supplies are out of tolerance, a fatal error shall occur.

Boot Handle Fatal Error
.......................

If a fatal error occurs during initialization, the AFCC shall attempt to output a diagnostic message to the CDT and halt initialization.

Background BIT
--------------

Perform Background BIT
......................

During normal operation of the AFCC, the AFCC shall perform background BIT of various system components.  Background BIT shall be performed during system idle time.

Background Process CPU and Software Exceptions
..............................................

During normal operation of the AFCC, the AFCC shall recognize all CPU and software exceptions.  If any exception occurs, a fatal error shall occur.

Background Test AFCC Controller Board DAC's
...........................................

During background BIT, the AFCC shall utilize the DAC test capability of the AFCC Controller board to verify that the DAC components of the AFCC Controller board are set to their last written values.  If any DAC component is not properly set, a fatal error shall occur.

Background Test AFCC Controller Board Relay and Discrete Outputs
................................................................

During background BIT, the AFCC shall utilize the relay and discrete output test capability of the AFCC Controller board to verify that the relay and discrete output components of the AFCC Controller board are set to their last written values.  If any relay or discrete output component is not properly set, a fatal error shall occur.

Perform RAM Checksum
....................

During background BIT, the AFCC shall checksum the code image to insure that it is correct.  If the checksum does not match the code image, a fatal error shall occur.

Background Monitor Voltages
...........................

During background BIT, the AFCC shall monitor the +5 volt, +15 volt, -15 volt, and +28 volt power supplies to insure that they are within tolerance.  If any of the power supplies are out of tolerance, a fatal error shall occur.

Background Handle Fatal Error
.............................

When the AFCC detects a fatal error, the following shall be attempted:

 a. light the fault light on the gunner console,

 b. stop the execution of all tasks,

 c. reset all hardware outputs to a safe state,

 d. store a failure code or message in the EEPROM,

 e. output a diagnostic message to the CDT and Console port,

 f. halt the system.