Please reference README.booting for the boot/load process. For the priority setting of the Interrupt Requests (IRQs), please reference README.irq The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release. I believe in valuable real-time programming, where technical neatness, performance and truth are. I hope I still believe. Any suggestion, bug reports, or even bug fixes (great!) would be highly appreciated so that I still believe what I believe. ACKNOWLEDGEMENTS ---------------- Acknowledgements: Valuable information was obtained from the following: 1) Marvell NDA document for the discovery system controller. Other related documents are listed at : http://www.aps.anl.gov/epics/meetings/2006-06/RTEMS_Primer_SIG/RTEMS_BSP_MVME5500.pdf 2) netBSD: For the two NICS and some headers : Allegro Networks, Inc., Wasabi Systems, Inc. 3) RTEMS: This BSP also builds on top of the work of others who have contributed to similar RTEMS powerpc shared and motorola_powerpc BSPs, most notably Eric Valette, Till Straumann (SVGM1 BSP, too), Eric Norum and others. LICENSE ------- See ./LICENSE file. BSP NAME: mvme5500 BOARD: MVME5500 by Motorola BUS: PCI CPU FAMILY: ppc CPU: MPC7455 @ 1GHZ COPROCESSORS: N/A MODE: 32/64 bit mode (support 32 bit for now) DEBUG MONITOR: MOTLoad SYSTEM CONTROLLER: GT64260B PERIPHERALS =========== TIMERS: Eight, 32 bit programmable SERIAL PORTS: 2 NS 16550 on GT64260B REAL-TIME CLOCK: MK48T37V 32K NVSRAM: MK48T37V WATCHDOG TIMER: use the one in GT-64260B DMA: 8 channel DMA controller (GT-64260B) VIDEO: none NETWORKING: Port 1: Intel 82544EI Gigabit Ethernet Controller 10/100/1000Mb/s routed to front panel RJ-45 Port 2: 10/100 Mb ethernet unit integrated on the Marvell's GT64260 system controller DRIVER INFORMATION ================== CLOCK DRIVER: PPC internal IOSUPP DRIVER: N/A SHMSUPP: N/A TIMER DRIVER: PPC internal TTY DRIVER: PPC internal STDIO ===== PORT: Console port 0 ELECTRICAL: na BAUD: na BITS PER CHARACTER: na PARITY: na STOP BITS: na Jumpers ======= 1) The BSP is tested with the 60x bus mode instead of the MPX bus mode. ( No jumper or a jumper across pins 1-2 on J19 selects the 60x bus mode) 2) On the mvme5500 board, Ethernet 1 is the Gigabit Ethernet port and is front panel only. Ethernet 2 is 10/100 BaseT Ethernet. For front-panel Ethernet2, install jumpers across pins 1-2 on all J6, J7, J100 and J101 headers. 3) Enable SROM initialization at startup. (No jumper or a jumper across pins 1-2 on J17) In fact, (if I did not miss anything) the mvme5500 board should function properly if one keeps all the jumpers at factory configuration. One can leave out the jumper on J30 to disable EEPROM programming. Notes ===== BSP BAT usage ---------------------- DBAT0 and IBAT0 0x00000000 0x0fffffff 1st 256M, for MEMORY access (caching enabled) DBAT1 and IBAT1 0x00000000 0x0fffffff 2nd 256M, for MEMORY access (caching enabled) UPDATE: (2004/5). The BSP now uses page tables for mapping the entire 512MB of RAM. DBAT0 and DBAT1 is hence free for use by the application. A simple 1:1 (virt<->phys) mapping is employed. The BSP write-protects the text and read-only data areas of the application. Special acknowledgement to Till Straumann for providing inputs in porting the memory protection software he wrote (BSP_pgtbl_xxx()) to MVME5500. The default VME configuration uses DBAT0 to map more PCI memory space for use by the universe VME bridge: DBAT0 0x90000000 PCI memory space <-> VME 0x9fffffff Port VME-Addr Size PCI-Adrs Mode: 0: 0x20000000 0x0F000000 0x90000000 A32, Dat, Sup 1: 0x00000000 0x00FF0000 0x9F000000 A24, Dat, Sup 2: 0x00000000 0x00010000 0x9FFF0000 A16, Dat, Sup