Changeset ffe6331 in rtems


Ignore:
Timestamp:
Mar 31, 2004, 3:46:24 AM (16 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
dac4208
Parents:
9347024
Message:

2004-03-31 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, ppccache.c: Convert to using c99 fixed size types.
Location:
c/src/lib
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/support/old_exception_processing/ChangeLog

    r9347024 rffe6331  
     12004-03-31      Ralf Corsepius <ralf_corsepius@rtems.org>
     2
     3        * cpu.c, ppccache.c: Convert to using c99 fixed size types.
     4
    152004-01-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    26
  • c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c

    r9347024 rffe6331  
    6464#endif
    6565#if (PPC_ABI != PPC_ABI_POWEROPEN)
    66   register unsigned32 r2 = 0;
     66  register uint32_t  r2 = 0;
    6767#if (PPC_ABI != PPC_ABI_GCC27)
    68   register unsigned32 r13 = 0;
     68  register uint32_t  r13 = 0;
    6969
    7070  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
     
    8080  /* fill in _CPU_IRQ_info.Vector_table later */
    8181#if (PPC_ABI == PPC_ABI_POWEROPEN)
    82   _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
     82  _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1];
    8383#endif
    8484  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
     
    139139 */
    140140 
    141 unsigned32 _CPU_ISR_Calculate_level(
    142   unsigned32 new_level
     141uint32_t  _CPU_ISR_Calculate_level(
     142  uint32_t  new_level
    143143)
    144144{
    145   register unsigned32 new_msr = 0;
     145  register uint32_t  new_msr = 0;
    146146
    147147  /*
     
    171171
    172172void _CPU_ISR_Set_level(
    173   unsigned32 new_level
     173  uint32_t  new_level
    174174)
    175175{
    176   register unsigned32 tmp = 0;
    177   register unsigned32 new_msr;
     176  register uint32_t  tmp = 0;
     177  register uint32_t  new_msr;
    178178
    179179  new_msr = _CPU_ISR_Calculate_level( new_level );
     
    194194 */
    195195
    196 unsigned32 _CPU_ISR_Get_level( void )
    197 {
    198   unsigned32 level = 0;
    199   unsigned32 msr;
     196uint32_t  _CPU_ISR_Get_level( void )
     197{
     198  uint32_t  level = 0;
     199  uint32_t  msr;
    200200 
    201201  asm volatile("mfmsr %0" : "=r" ((msr)));
     
    234234void _CPU_Context_Initialize(
    235235  Context_Control  *the_context,
    236   unsigned32       *stack_base,
    237   unsigned32        size,
    238   unsigned32        new_level,
     236  uint32_t         *stack_base,
     237  uint32_t          size,
     238  uint32_t          new_level,
    239239  void             *entry_point,
    240240  boolean           is_fp
    241241)
    242242{
    243   unsigned32 msr_value;
    244   unsigned32 sp;
    245 
    246   sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
    247   *((unsigned32 *)sp) = 0;
     243  uint32_t  msr_value;
     244  uint32_t  sp;
     245
     246  sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
     247  *((uint32_t*)sp) = 0;
    248248  the_context->gpr1 = sp;
    249249   
     
    275275
    276276#if (PPC_ABI == PPC_ABI_POWEROPEN)
    277   { unsigned32 *desc = (unsigned32 *)entry_point;
     277  { uint32_t   *desc = (uint32_t*)entry_point;
    278278
    279279    the_context->pc = desc[0];
     
    286286    asm volatile ("mr %0, 13" : "=r" ((r13)));
    287287   
    288     the_context->pc = (unsigned32)entry_point;
     288    the_context->pc = (uint32_t)entry_point;
    289289    the_context->gpr13 = r13;
    290290  }
     
    292292
    293293#if (PPC_ABI == PPC_ABI_EABI)
    294   { unsigned32  r2 = 0;
     294  { uint32_t    r2 = 0;
    295295    unsigned    r13 = 0;
    296296    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
    297297 
    298     the_context->pc = (unsigned32)entry_point;
     298    the_context->pc = (uint32_t)entry_point;
    299299    the_context->gpr2 = r2;
    300300    the_context->gpr13 = r13;
     
    319319
    320320void _CPU_ISR_install_vector(
    321   unsigned32  vector,
     321  uint32_t    vector,
    322322  proc_ptr    new_handler,
    323323  proc_ptr   *old_handler
     
    398398}
    399399
    400 void _CPU_Fatal_error(unsigned32 _error)
     400void _CPU_Fatal_error(uint32_t  _error)
    401401{
    402402  asm volatile ("mr 3, %0" : : "r" ((_error)));
     
    441441#endif /* mpc860 */
    442442
    443 unsigned32  ppc_exception_vector_addr(
    444   unsigned32 vector
     443uint32_t    ppc_exception_vector_addr(
     444  uint32_t  vector
    445445);
    446446
     
    473473 
    474474void _CPU_ISR_install_raw_handler(
    475   unsigned32  vector,
     475  uint32_t    vector,
    476476  proc_ptr    new_handler,
    477477  proc_ptr   *old_handler
    478478)
    479479{
    480   unsigned32             real_vector;
     480  uint32_t               real_vector;
    481481  CPU_Trap_table_entry  *slot;
    482   unsigned32             u32_handler=0;
     482  uint32_t               u32_handler=0;
    483483
    484484  /*
     
    546546  *slot = _CPU_Trap_slot_template;
    547547
    548   u32_handler = (unsigned32) new_handler;
     548  u32_handler = (uint32_t) new_handler;
    549549
    550550  /*
     
    569569}
    570570
    571 unsigned32  ppc_exception_vector_addr(
    572   unsigned32 vector
     571uint32_t    ppc_exception_vector_addr(
     572  uint32_t  vector
    573573)
    574574{
    575575#if (!PPC_HAS_EVPR)
    576   unsigned32 Msr;
    577 #endif
    578   unsigned32 Top = 0;
    579   unsigned32 Offset = 0x000;
     576  uint32_t  Msr;
     577#endif
     578  uint32_t  Top = 0;
     579  uint32_t  Offset = 0x000;
    580580
    581581#if (PPC_HAS_EXCEPTION_PREFIX)
  • c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c

    r9347024 rffe6331  
    3232void powerpc_instruction_cache_enable ()
    3333{
    34   unsigned32 value;
     34  uint32_t  value;
    3535
    3636  /*
     
    4747void powerpc_data_cache_enable ()
    4848{
    49   unsigned32 value;
     49  uint32_t  value;
    5050
    5151  /*
  • c/src/lib/libcpu/powerpc/old-exceptions/ChangeLog

    r9347024 rffe6331  
     12004-03-31      Ralf Corsepius <ralf_corsepius@rtems.org>
     2
     3        * cpu.c, ppccache.c: Convert to using c99 fixed size types.
     4
    152004-01-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    26
  • c/src/lib/libcpu/powerpc/old-exceptions/cpu.c

    r9347024 rffe6331  
    6464#endif
    6565#if (PPC_ABI != PPC_ABI_POWEROPEN)
    66   register unsigned32 r2 = 0;
     66  register uint32_t  r2 = 0;
    6767#if (PPC_ABI != PPC_ABI_GCC27)
    68   register unsigned32 r13 = 0;
     68  register uint32_t  r13 = 0;
    6969
    7070  asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13)));
     
    8080  /* fill in _CPU_IRQ_info.Vector_table later */
    8181#if (PPC_ABI == PPC_ABI_POWEROPEN)
    82   _CPU_IRQ_info.Dispatch_r2 = ((unsigned32 *)_Thread_Dispatch)[1];
     82  _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1];
    8383#endif
    8484  _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary;
     
    139139 */
    140140 
    141 unsigned32 _CPU_ISR_Calculate_level(
    142   unsigned32 new_level
     141uint32_t  _CPU_ISR_Calculate_level(
     142  uint32_t  new_level
    143143)
    144144{
    145   register unsigned32 new_msr = 0;
     145  register uint32_t  new_msr = 0;
    146146
    147147  /*
     
    171171
    172172void _CPU_ISR_Set_level(
    173   unsigned32 new_level
     173  uint32_t  new_level
    174174)
    175175{
    176   register unsigned32 tmp = 0;
    177   register unsigned32 new_msr;
     176  register uint32_t  tmp = 0;
     177  register uint32_t  new_msr;
    178178
    179179  new_msr = _CPU_ISR_Calculate_level( new_level );
     
    194194 */
    195195
    196 unsigned32 _CPU_ISR_Get_level( void )
    197 {
    198   unsigned32 level = 0;
    199   unsigned32 msr;
     196uint32_t  _CPU_ISR_Get_level( void )
     197{
     198  uint32_t  level = 0;
     199  uint32_t  msr;
    200200 
    201201  asm volatile("mfmsr %0" : "=r" ((msr)));
     
    234234void _CPU_Context_Initialize(
    235235  Context_Control  *the_context,
    236   unsigned32       *stack_base,
    237   unsigned32        size,
    238   unsigned32        new_level,
     236  uint32_t         *stack_base,
     237  uint32_t          size,
     238  uint32_t          new_level,
    239239  void             *entry_point,
    240240  boolean           is_fp
    241241)
    242242{
    243   unsigned32 msr_value;
    244   unsigned32 sp;
    245 
    246   sp = (unsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
    247   *((unsigned32 *)sp) = 0;
     243  uint32_t  msr_value;
     244  uint32_t  sp;
     245
     246  sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;
     247  *((uint32_t*)sp) = 0;
    248248  the_context->gpr1 = sp;
    249249   
     
    275275
    276276#if (PPC_ABI == PPC_ABI_POWEROPEN)
    277   { unsigned32 *desc = (unsigned32 *)entry_point;
     277  { uint32_t   *desc = (uint32_t*)entry_point;
    278278
    279279    the_context->pc = desc[0];
     
    286286    asm volatile ("mr %0, 13" : "=r" ((r13)));
    287287   
    288     the_context->pc = (unsigned32)entry_point;
     288    the_context->pc = (uint32_t)entry_point;
    289289    the_context->gpr13 = r13;
    290290  }
     
    292292
    293293#if (PPC_ABI == PPC_ABI_EABI)
    294   { unsigned32  r2 = 0;
     294  { uint32_t    r2 = 0;
    295295    unsigned    r13 = 0;
    296296    asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13)));
    297297 
    298     the_context->pc = (unsigned32)entry_point;
     298    the_context->pc = (uint32_t)entry_point;
    299299    the_context->gpr2 = r2;
    300300    the_context->gpr13 = r13;
     
    319319
    320320void _CPU_ISR_install_vector(
    321   unsigned32  vector,
     321  uint32_t    vector,
    322322  proc_ptr    new_handler,
    323323  proc_ptr   *old_handler
     
    398398}
    399399
    400 void _CPU_Fatal_error(unsigned32 _error)
     400void _CPU_Fatal_error(uint32_t  _error)
    401401{
    402402  asm volatile ("mr 3, %0" : : "r" ((_error)));
     
    441441#endif /* mpc860 */
    442442
    443 unsigned32  ppc_exception_vector_addr(
    444   unsigned32 vector
     443uint32_t    ppc_exception_vector_addr(
     444  uint32_t  vector
    445445);
    446446
     
    473473 
    474474void _CPU_ISR_install_raw_handler(
    475   unsigned32  vector,
     475  uint32_t    vector,
    476476  proc_ptr    new_handler,
    477477  proc_ptr   *old_handler
    478478)
    479479{
    480   unsigned32             real_vector;
     480  uint32_t               real_vector;
    481481  CPU_Trap_table_entry  *slot;
    482   unsigned32             u32_handler=0;
     482  uint32_t               u32_handler=0;
    483483
    484484  /*
     
    546546  *slot = _CPU_Trap_slot_template;
    547547
    548   u32_handler = (unsigned32) new_handler;
     548  u32_handler = (uint32_t) new_handler;
    549549
    550550  /*
     
    569569}
    570570
    571 unsigned32  ppc_exception_vector_addr(
    572   unsigned32 vector
     571uint32_t    ppc_exception_vector_addr(
     572  uint32_t  vector
    573573)
    574574{
    575575#if (!PPC_HAS_EVPR)
    576   unsigned32 Msr;
    577 #endif
    578   unsigned32 Top = 0;
    579   unsigned32 Offset = 0x000;
     576  uint32_t  Msr;
     577#endif
     578  uint32_t  Top = 0;
     579  uint32_t  Offset = 0x000;
    580580
    581581#if (PPC_HAS_EXCEPTION_PREFIX)
  • c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c

    r9347024 rffe6331  
    3232void powerpc_instruction_cache_enable ()
    3333{
    34   unsigned32 value;
     34  uint32_t  value;
    3535
    3636  /*
     
    4747void powerpc_data_cache_enable ()
    4848{
    49   unsigned32 value;
     49  uint32_t  value;
    5050
    5151  /*
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