Changeset ffe6331 in rtems
- Timestamp:
- 03/31/04 03:46:24 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- dac4208
- Parents:
- 9347024
- Location:
- c/src/lib
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/support/old_exception_processing/ChangeLog
r9347024 rffe6331 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, ppccache.c: Convert to using c99 fixed size types. 4 1 5 2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 6 -
c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c
r9347024 rffe6331 64 64 #endif 65 65 #if (PPC_ABI != PPC_ABI_POWEROPEN) 66 register u nsigned32r2 = 0;66 register uint32_t r2 = 0; 67 67 #if (PPC_ABI != PPC_ABI_GCC27) 68 register u nsigned32r13 = 0;68 register uint32_t r13 = 0; 69 69 70 70 asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); … … 80 80 /* fill in _CPU_IRQ_info.Vector_table later */ 81 81 #if (PPC_ABI == PPC_ABI_POWEROPEN) 82 _CPU_IRQ_info.Dispatch_r2 = ((u nsigned32*)_Thread_Dispatch)[1];82 _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1]; 83 83 #endif 84 84 _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; … … 139 139 */ 140 140 141 u nsigned32_CPU_ISR_Calculate_level(142 u nsigned32new_level141 uint32_t _CPU_ISR_Calculate_level( 142 uint32_t new_level 143 143 ) 144 144 { 145 register u nsigned32new_msr = 0;145 register uint32_t new_msr = 0; 146 146 147 147 /* … … 171 171 172 172 void _CPU_ISR_Set_level( 173 u nsigned32new_level173 uint32_t new_level 174 174 ) 175 175 { 176 register u nsigned32tmp = 0;177 register u nsigned32new_msr;176 register uint32_t tmp = 0; 177 register uint32_t new_msr; 178 178 179 179 new_msr = _CPU_ISR_Calculate_level( new_level ); … … 194 194 */ 195 195 196 u nsigned32_CPU_ISR_Get_level( void )197 { 198 u nsigned32level = 0;199 u nsigned32msr;196 uint32_t _CPU_ISR_Get_level( void ) 197 { 198 uint32_t level = 0; 199 uint32_t msr; 200 200 201 201 asm volatile("mfmsr %0" : "=r" ((msr))); … … 234 234 void _CPU_Context_Initialize( 235 235 Context_Control *the_context, 236 u nsigned32*stack_base,237 u nsigned32size,238 u nsigned32new_level,236 uint32_t *stack_base, 237 uint32_t size, 238 uint32_t new_level, 239 239 void *entry_point, 240 240 boolean is_fp 241 241 ) 242 242 { 243 u nsigned32msr_value;244 u nsigned32sp;245 246 sp = (u nsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;247 *((u nsigned32*)sp) = 0;243 uint32_t msr_value; 244 uint32_t sp; 245 246 sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE; 247 *((uint32_t*)sp) = 0; 248 248 the_context->gpr1 = sp; 249 249 … … 275 275 276 276 #if (PPC_ABI == PPC_ABI_POWEROPEN) 277 { u nsigned32 *desc = (unsigned32*)entry_point;277 { uint32_t *desc = (uint32_t*)entry_point; 278 278 279 279 the_context->pc = desc[0]; … … 286 286 asm volatile ("mr %0, 13" : "=r" ((r13))); 287 287 288 the_context->pc = (u nsigned32)entry_point;288 the_context->pc = (uint32_t)entry_point; 289 289 the_context->gpr13 = r13; 290 290 } … … 292 292 293 293 #if (PPC_ABI == PPC_ABI_EABI) 294 { u nsigned32r2 = 0;294 { uint32_t r2 = 0; 295 295 unsigned r13 = 0; 296 296 asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); 297 297 298 the_context->pc = (u nsigned32)entry_point;298 the_context->pc = (uint32_t)entry_point; 299 299 the_context->gpr2 = r2; 300 300 the_context->gpr13 = r13; … … 319 319 320 320 void _CPU_ISR_install_vector( 321 u nsigned32vector,321 uint32_t vector, 322 322 proc_ptr new_handler, 323 323 proc_ptr *old_handler … … 398 398 } 399 399 400 void _CPU_Fatal_error(u nsigned32_error)400 void _CPU_Fatal_error(uint32_t _error) 401 401 { 402 402 asm volatile ("mr 3, %0" : : "r" ((_error))); … … 441 441 #endif /* mpc860 */ 442 442 443 u nsigned32ppc_exception_vector_addr(444 u nsigned32vector443 uint32_t ppc_exception_vector_addr( 444 uint32_t vector 445 445 ); 446 446 … … 473 473 474 474 void _CPU_ISR_install_raw_handler( 475 u nsigned32vector,475 uint32_t vector, 476 476 proc_ptr new_handler, 477 477 proc_ptr *old_handler 478 478 ) 479 479 { 480 u nsigned32real_vector;480 uint32_t real_vector; 481 481 CPU_Trap_table_entry *slot; 482 u nsigned32u32_handler=0;482 uint32_t u32_handler=0; 483 483 484 484 /* … … 546 546 *slot = _CPU_Trap_slot_template; 547 547 548 u32_handler = (u nsigned32) new_handler;548 u32_handler = (uint32_t) new_handler; 549 549 550 550 /* … … 569 569 } 570 570 571 u nsigned32ppc_exception_vector_addr(572 u nsigned32vector571 uint32_t ppc_exception_vector_addr( 572 uint32_t vector 573 573 ) 574 574 { 575 575 #if (!PPC_HAS_EVPR) 576 u nsigned32Msr;577 #endif 578 u nsigned32Top = 0;579 u nsigned32Offset = 0x000;576 uint32_t Msr; 577 #endif 578 uint32_t Top = 0; 579 uint32_t Offset = 0x000; 580 580 581 581 #if (PPC_HAS_EXCEPTION_PREFIX) -
c/src/lib/libbsp/powerpc/support/old_exception_processing/ppccache.c
r9347024 rffe6331 32 32 void powerpc_instruction_cache_enable () 33 33 { 34 u nsigned32value;34 uint32_t value; 35 35 36 36 /* … … 47 47 void powerpc_data_cache_enable () 48 48 { 49 u nsigned32value;49 uint32_t value; 50 50 51 51 /* -
c/src/lib/libcpu/powerpc/old-exceptions/ChangeLog
r9347024 rffe6331 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, ppccache.c: Convert to using c99 fixed size types. 4 1 5 2004-01-30 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 6 -
c/src/lib/libcpu/powerpc/old-exceptions/cpu.c
r9347024 rffe6331 64 64 #endif 65 65 #if (PPC_ABI != PPC_ABI_POWEROPEN) 66 register u nsigned32r2 = 0;66 register uint32_t r2 = 0; 67 67 #if (PPC_ABI != PPC_ABI_GCC27) 68 register u nsigned32r13 = 0;68 register uint32_t r13 = 0; 69 69 70 70 asm ("mr %0,13" : "=r" ((r13)) : "0" ((r13))); … … 80 80 /* fill in _CPU_IRQ_info.Vector_table later */ 81 81 #if (PPC_ABI == PPC_ABI_POWEROPEN) 82 _CPU_IRQ_info.Dispatch_r2 = ((u nsigned32*)_Thread_Dispatch)[1];82 _CPU_IRQ_info.Dispatch_r2 = ((uint32_t*)_Thread_Dispatch)[1]; 83 83 #endif 84 84 _CPU_IRQ_info.Switch_necessary = &_Context_Switch_necessary; … … 139 139 */ 140 140 141 u nsigned32_CPU_ISR_Calculate_level(142 u nsigned32new_level141 uint32_t _CPU_ISR_Calculate_level( 142 uint32_t new_level 143 143 ) 144 144 { 145 register u nsigned32new_msr = 0;145 register uint32_t new_msr = 0; 146 146 147 147 /* … … 171 171 172 172 void _CPU_ISR_Set_level( 173 u nsigned32new_level173 uint32_t new_level 174 174 ) 175 175 { 176 register u nsigned32tmp = 0;177 register u nsigned32new_msr;176 register uint32_t tmp = 0; 177 register uint32_t new_msr; 178 178 179 179 new_msr = _CPU_ISR_Calculate_level( new_level ); … … 194 194 */ 195 195 196 u nsigned32_CPU_ISR_Get_level( void )197 { 198 u nsigned32level = 0;199 u nsigned32msr;196 uint32_t _CPU_ISR_Get_level( void ) 197 { 198 uint32_t level = 0; 199 uint32_t msr; 200 200 201 201 asm volatile("mfmsr %0" : "=r" ((msr))); … … 234 234 void _CPU_Context_Initialize( 235 235 Context_Control *the_context, 236 u nsigned32*stack_base,237 u nsigned32size,238 u nsigned32new_level,236 uint32_t *stack_base, 237 uint32_t size, 238 uint32_t new_level, 239 239 void *entry_point, 240 240 boolean is_fp 241 241 ) 242 242 { 243 u nsigned32msr_value;244 u nsigned32sp;245 246 sp = (u nsigned32)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE;247 *((u nsigned32*)sp) = 0;243 uint32_t msr_value; 244 uint32_t sp; 245 246 sp = (uint32_t)stack_base + size - CPU_MINIMUM_STACK_FRAME_SIZE; 247 *((uint32_t*)sp) = 0; 248 248 the_context->gpr1 = sp; 249 249 … … 275 275 276 276 #if (PPC_ABI == PPC_ABI_POWEROPEN) 277 { u nsigned32 *desc = (unsigned32*)entry_point;277 { uint32_t *desc = (uint32_t*)entry_point; 278 278 279 279 the_context->pc = desc[0]; … … 286 286 asm volatile ("mr %0, 13" : "=r" ((r13))); 287 287 288 the_context->pc = (u nsigned32)entry_point;288 the_context->pc = (uint32_t)entry_point; 289 289 the_context->gpr13 = r13; 290 290 } … … 292 292 293 293 #if (PPC_ABI == PPC_ABI_EABI) 294 { u nsigned32r2 = 0;294 { uint32_t r2 = 0; 295 295 unsigned r13 = 0; 296 296 asm volatile ("mr %0,2; mr %1,13" : "=r" ((r2)), "=r" ((r13))); 297 297 298 the_context->pc = (u nsigned32)entry_point;298 the_context->pc = (uint32_t)entry_point; 299 299 the_context->gpr2 = r2; 300 300 the_context->gpr13 = r13; … … 319 319 320 320 void _CPU_ISR_install_vector( 321 u nsigned32vector,321 uint32_t vector, 322 322 proc_ptr new_handler, 323 323 proc_ptr *old_handler … … 398 398 } 399 399 400 void _CPU_Fatal_error(u nsigned32_error)400 void _CPU_Fatal_error(uint32_t _error) 401 401 { 402 402 asm volatile ("mr 3, %0" : : "r" ((_error))); … … 441 441 #endif /* mpc860 */ 442 442 443 u nsigned32ppc_exception_vector_addr(444 u nsigned32vector443 uint32_t ppc_exception_vector_addr( 444 uint32_t vector 445 445 ); 446 446 … … 473 473 474 474 void _CPU_ISR_install_raw_handler( 475 u nsigned32vector,475 uint32_t vector, 476 476 proc_ptr new_handler, 477 477 proc_ptr *old_handler 478 478 ) 479 479 { 480 u nsigned32real_vector;480 uint32_t real_vector; 481 481 CPU_Trap_table_entry *slot; 482 u nsigned32u32_handler=0;482 uint32_t u32_handler=0; 483 483 484 484 /* … … 546 546 *slot = _CPU_Trap_slot_template; 547 547 548 u32_handler = (u nsigned32) new_handler;548 u32_handler = (uint32_t) new_handler; 549 549 550 550 /* … … 569 569 } 570 570 571 u nsigned32ppc_exception_vector_addr(572 u nsigned32vector571 uint32_t ppc_exception_vector_addr( 572 uint32_t vector 573 573 ) 574 574 { 575 575 #if (!PPC_HAS_EVPR) 576 u nsigned32Msr;577 #endif 578 u nsigned32Top = 0;579 u nsigned32Offset = 0x000;576 uint32_t Msr; 577 #endif 578 uint32_t Top = 0; 579 uint32_t Offset = 0x000; 580 580 581 581 #if (PPC_HAS_EXCEPTION_PREFIX) -
c/src/lib/libcpu/powerpc/old-exceptions/ppccache.c
r9347024 rffe6331 32 32 void powerpc_instruction_cache_enable () 33 33 { 34 u nsigned32value;34 uint32_t value; 35 35 36 36 /* … … 47 47 void powerpc_data_cache_enable () 48 48 { 49 u nsigned32value;49 uint32_t value; 50 50 51 51 /*
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