Index: src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S
===================================================================
--- c/src/lib/libcpu/powerpc/mpc6xx/exceptions/asm_utils.S	(revision 7dbc43da43901228713d12d5deab637d2c9af820)
+++ 	(revision )
@@ -1,62 +1,0 @@
-/*
- *  asm_utils.s
- *
- *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
- *
- *  This file contains the low-level support for moving exception
- *  exception code to appropriate location.
- *
- */
-
-#include <rtems/asm.h>
-#include <rtems/score/cpu.h>
-#include <libcpu/io.h>
-
-	.globl  codemove
-codemove:
-	.type	codemove,@function
-/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
-	cmplw	cr1,r3,r4
-	addi	r0,r5,3
-	srwi.	r0,r0,2
-	beq	cr1,4f	/* In place copy is not necessary */
-	beq	7f	/* Protect against 0 count */
-	mtctr	r0
-	bge	cr1,2f
-
-	la	r8,-4(r4)
-	la	r7,-4(r3)
-1:	lwzu	r0,4(r8)
-	stwu	r0,4(r7)
-	bdnz	1b
-	b	4f
-
-2:	slwi	r0,r0,2
-	add	r8,r4,r0
-	add	r7,r3,r0
-3:	lwzu	r0,-4(r8)
-	stwu	r0,-4(r7)
-	bdnz	3b
-
-/* Now flush the cache:	note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4:	cmpwi	r6,0
-	add	r5,r3,r5
-	beq	7f	/* Always flush prefetch queue in any case */
-	subi	r0,r6,1
-	andc	r3,r3,r0
-	mr	r4,r3
-5:	cmplw	r4,r5
-	dcbst	0,r4
-	add	r4,r4,r6
-	blt	5b
-	sync		/* Wait for all dcbst to complete on bus */
-	mr	r4,r3
-6:	cmplw	r4,r5
-	icbi	0,r4
-	add	r4,r4,r6
-	blt	6b
-7:	sync		/* Wait for all icbi to complete on bus */
-	isync
-	blr
Index: src/lib/libcpu/powerpc/new-exceptions/asm_utils.S
===================================================================
--- c/src/lib/libcpu/powerpc/new-exceptions/asm_utils.S	(revision 7dbc43da43901228713d12d5deab637d2c9af820)
+++ 	(revision )
@@ -1,61 +1,0 @@
-/*
- *  asm_utils.s
- *
- *  Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
- *
- *  This file contains the low-level support for moving exception
- *  exception code to appropriate location.
- *
- */
-
-#include <rtems/asm.h>
-#include <rtems/score/cpu.h>
-
-	.globl  codemove
-codemove:
-	.type	codemove,@function
-/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */
-	cmplw	cr1,r3,r4
-	addi	r0,r5,3
-	srwi.	r0,r0,2
-	beq	cr1,4f	/* In place copy is not necessary */
-	beq	7f	/* Protect against 0 count */
-	mtctr	r0
-	bge	cr1,2f
-
-	la	r8,-4(r4)
-	la	r7,-4(r3)
-1:	lwzu	r0,4(r8)
-	stwu	r0,4(r7)
-	bdnz	1b
-	b	4f
-
-2:	slwi	r0,r0,2
-	add	r8,r4,r0
-	add	r7,r3,r0
-3:	lwzu	r0,-4(r8)
-	stwu	r0,-4(r7)
-	bdnz	3b
-
-/* Now flush the cache:	note that we must start from a cache aligned
- * address. Otherwise we might miss one cache line.
- */
-4:	cmpwi	r6,0
-	add	r5,r3,r5
-	beq	7f	/* Always flush prefetch queue in any case */
-	subi	r0,r6,1
-	andc	r3,r3,r0
-	mr	r4,r3
-5:	cmplw	r4,r5
-	dcbst	0,r4
-	add	r4,r4,r6
-	blt	5b
-	sync		/* Wait for all dcbst to complete on bus */
-	mr	r4,r3
-6:	cmplw	r4,r5
-	icbi	0,r4
-	add	r4,r4,r6
-	blt	6b
-7:	sync		/* Wait for all icbi to complete on bus */
-	isync
-	blr
Index: src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c
===================================================================
--- c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/nested_irq_test.c	(revision 7dbc43da43901228713d12d5deab637d2c9af820)
+++ 	(revision )
@@ -1,105 +1,0 @@
-/*
- * Test nested interrupts.
- *
- * Author: Till Straumann <strauman@slac.stanford.edu>, 2007
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-
-/*
- * Needs board with 2 available openpic timers
- *
- * 'timer_instdis(timer, install, period)'
- *
- * installs 'timer_isr' to openpic timer # 'timer'.
- * The interrupt priority is set to 8 + timer#
- *
- * The timer_isr prints a message then polls
- * the variable 'timer_poll' while it has the value
- * of the timer # then sets it to -1 and prints
- * the 'leave' message.
- *
- * To test nested interrupts:
- *
- *  timer_instdis(0, 1, period)
- *  wait_a_bit()
- *  timer_instdis(1, 1, period)
- *  timer_poll = 0;
- *
- *  As soon as timer 0's IRQ fires the
- *  isr prints
- *     TIMER ISR (0) ...
- *  then starts polling (since timer_poll == 0 )
- *  eventually, timer 1 goes off, interrupts (because
- *  it's priority is 9 (i.e., higher than timer 0's priority)
- *  and prints
- *     TIMER ISR (1)
- *  it skips polling since timer_poll is 0, not 1 but
- *  resets timer_poll -1 and prints
- *     Leaving ISR (1)
- *  timer 0 isr resumes polling and finds timer_poll == -1
- *  so it also writes -1 to timer_poll and exits, printing
- *     Leaving ISR (0)
- *
- *  The timer IRQs can be unhooked with
- *     timer_instdis( 0, 0, period );
- *     timer_instdis( 1, 0, period );
- */
-#include <rtems.h>
-#include <rtems/bspIo.h>
-#include <bsp/openpic.h>
-#include <bsp/irq.h>
-#include <inttypes.h>
-#include <stdio.h>
-
-volatile int timer_poll=-1;
-
-static void timer_isr(rtems_irq_hdl_param p)
-{
-uint32_t top;
-uint32_t r1;
-uint32_t lat = (OpenPIC->Global.Timer[(int)p].Current_Count & 0x7fffffff);
-
-	lat = OpenPIC->Global.Timer[(int)p].Base_Count - lat;
-
-	asm volatile("mfspr %0, %2; mr %1, 1":"=r"(top),"=r"(r1):"i"(SPRG1));
-	printk("Timer ISR (%i): LAT: 0x%08x, TOP 0x%08x, BOT 0x%08x, SP 0x%08x\n",
-		(int)p, lat, top, top-rtems_configuration_get_interrupt_stack_size(), r1);
-	printk("_ISR_Nest_level %i\n", _ISR_Nest_level);
-	while ( timer_poll == (int)p )
-		;
-	timer_poll = -1;
-
-	printk("Leaving ISR (%i)\n",(int)p);
-}
-
-int timer_instdis(int t, int inst, unsigned period)
-{
-rtems_irq_connect_data xx;
-	xx.name   = BSP_MISC_IRQ_LOWEST_OFFSET + t;
-	xx.hdl    = timer_isr;
-	xx.handle = (rtems_irq_hdl_param)t;
-	xx.on     = 0;
-	xx.off    = 0;
-	xx.isOn   = 0;
-	if ( !inst ) {
-		openpic_maptimer(t, 0);
-		openpic_inittimer(t, 0, 0);
-	}
-	if ( ! ( inst ? BSP_install_rtems_irq_handler(&xx) : BSP_remove_rtems_irq_handler(&xx) ) ) {
-		openpic_maptimer(t, 0);
-		openpic_inittimer(t, 0, 0);
-		fprintf(stderr,"unable to %s timer ISR #%i\n", inst ? "install" : "remove", t);
-		return -1;
-	}
-	if ( inst ) {
-		openpic_maptimer( t, 1 );
-		openpic_inittimer( t, 8 + t, OPENPIC_VEC_SOURCE - BSP_PCI_IRQ_LOWEST_OFFSET + xx.name );
-		openpic_settimer( t, period, 1 );
-	}
-	return 0;
-}
-
Index: src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_test.c
===================================================================
--- c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_test.c	(revision 7dbc43da43901228713d12d5deab637d2c9af820)
+++ 	(revision )
@@ -1,236 +1,0 @@
-/*
- * Test low-level exception handling code:
- *
- *  - hook an exception handler
- *  - clobber (almost) all registers with a known value
- *  - raise exception
- *  - from exception handler, increment all saved register
- *    contents by one (to ensure registers are not only
- *    saved properly but also restored properly).
- *  - resume execution
- *  - verify registers are now 'clobber_value + 1'
- *
- * NOTE: cannot be used on PSIM because SYS exception is used
- *       internally by simulator (but we could use a trap or
- *       something else).
- *
- * Author: Till Straumann <strauman@slac.stanford.edu>, 2007
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-
-#include <inttypes.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include "vectors.h"
-
-
-typedef struct regs_ {
-	uint32_t	cr, xer, lr, ctr;
-	uint32_t	gpr0;
-	uint32_t	gpr1;
-	uint32_t	gpr2;
-	uint32_t	gpr3;
-	uint32_t	gpr4;
-	uint32_t	gpr5;
-	uint32_t	gpr6;
-	uint32_t	gpr7;
-	uint32_t	gpr8;
-	uint32_t	gpr9;
-	uint32_t	gpr10;
-	uint32_t	gpr11;
-	uint32_t	gpr12;
-	uint32_t	gpr13;
-	uint32_t	gpr14;
-	uint32_t	gpr15;
-	uint32_t	gpr16;
-	uint32_t	gpr17;
-	uint32_t	gpr18;
-	uint32_t	gpr19;
-	uint32_t	gpr20;
-	uint32_t	gpr21;
-	uint32_t	gpr22;
-	uint32_t	gpr23;
-	uint32_t	gpr24;
-	uint32_t	gpr25;
-	uint32_t	gpr26;
-	uint32_t	gpr27;
-	uint32_t	gpr28;
-	uint32_t	gpr29;
-	uint32_t	gpr30;
-	uint32_t	gpr31;
-} ppc_exc_int_regs;
-
-#define OFF(x)	(uintptr_t)(&((ppc_exc_int_regs*)0)->x)
-
-void
-storegs(ppc_exc_int_regs *p0, ppc_exc_int_regs *p1)
-{
-	asm volatile(
-		"	stmw 0, %6(%0)   ;"
-		"	mfcr	0		 ;"
-		"	stw	 0, %2(%0)   ;"
-		"	mflr	0		 ;"
-		"	stw	 0, %3(%0)   ;"
-		"	mfxer	0		 ;"
-		"	stw	 0, %4(%0)   ;"
-		"	mfctr	0		 ;"
-		"	stw	 0, %5(%0)   ;"
-		"	lwz  0, %6(%0)   ;"
-		"	trap             ;"
-		"	stmw 0, %6(%1)   ;"
-		"	mfcr	0		 ;"
-		"	stw	 0, %2(%1)   ;"
-		"	mflr	0		 ;"
-		"	stw	 0, %3(%1)   ;"
-		"	mfxer	0		 ;"
-		"	stw	 0, %4(%1)   ;"
-		"	mfctr	0		 ;"
-		"	stw	 0, %5(%1)   ;"
-		:
-		:"b"(p0),"b"(p1),
-		"i"(OFF(cr)), "i"(OFF(lr)), "i"(OFF(xer)), "i"(OFF(ctr)),
-		"i"(OFF(gpr0))
-		:"r0");
-}
-
-/* Load up all registers from 'pre' issue system call and store
- * registers in 'post'
- */
-
-ppc_exc_int_regs pre;
-ppc_exc_int_regs pst;
-
-void
-clobber()
-{
-	asm volatile(
-		"	lis 2,  pre@h  ;"
-		"   ori 2, 2, pre@l  ;"
-		"	lwz	3,	%0(2) ;"
-		"	mtcr	3      ;"
-		"	lwz	3,	%1(2) ;"
-		"	mtlr	3      ;"
-		"	lwz	3,	%2(2) ;"
-		"	mtxer   3      ;"
-		/* don't know which ones stick */
-		"	mfxer   3      ;"
-		"   stw 3,  %2(2)  ;"
-		"	lwz	3,	%3(2) ;"
-		"	mtctr	3      ;"
-		"	lwz	0,	%4(2) ;"
-		/* must not clobber R13, R1, R2 */
-		"	stw 13, %6(2) ;"
-		"   lmw 3,  %5(2)  ;"
-		"   trap           ;"
-		"   stmw 0, %4(2) ;"
-		"	mfcr	0	   ;"
-		"	stw	 0, %0(2) ;"
-		"	mflr	0	   ;"
-		"	stw	 0, %1(2) ;"
-		"	mfxer	0	   ;"
-		"	stw	 0, %2(2) ;"
-		"	mfctr	0	   ;"
-		"	stw	 0, %3(2) ;"
-		:
-		:"i"(OFF(cr)), "i"(OFF(lr)), "i"(OFF(xer)), "i"(OFF(ctr)),
-		 "i"(OFF(gpr0)), "i"(OFF(gpr3)), "i"(OFF(gpr13))
-		:"r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9",
-		 "r10", "r11", "r12", "r14", "r15", "r16",
-		 "r17", "r18", "r19", "r20", "r21", "r22", "r23",
-		 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
-		 "xer","lr","ctr",
-		 "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7",
-		 "memory");
-}
-
-typedef union { uint32_t u; uint8_t c[4]; } u32_a_t;
-
-/* exception handler; adds 1 to all register contents (except r1,r2,r13) */
-int
-handle_clobber_exc(BSP_Exception_frame *f, unsigned vector)
-{
-int i;
-u32_a_t *p = (u32_a_t*)&f->GPR0;
-	for ( i=0; i<32; i++ ) {
-		switch (i) {
-			case 1: case 2: case 13: break;
-			default:
-				p[i].u++;
-			break;
-		}
-	}
-  f->GPR2 = (uint32_t)&pst;
-  f->EXC_CR++;
-  f->EXC_CTR++;
-  f->EXC_XER++;
-  f->EXC_LR++;
-  f->EXC_SRR0 += 4;
-  return 0;
-}
-
-
-/* This routine tests the raw exception code;
- *  - hook 'handle_clobber_exc' to SYS exception handler
- *  - clobber all registers with 0xaffe0000 + <index>
- *    (except: r1, r2, r13, non-sticky bits in xer)
- *    R2 is clobbered with the address of the pre area.
- *  - issue 'trap' -> PROG exception
- *  - exception handler increments all reg. contents by 1,
- *    stores address of 'pst' area in R2 and returns control
- *    to ppc_exc_clobber().
- *  - save all register contents to *R2 (should be &pst).
- *  - test for mismatches (except R1, R2, R13 and parts of xer)
- */
-void
-ppc_exc_clobber()
-{
-u32_a_t *a, *b;
-	int i;
-	a = (u32_a_t*)&pre;
-	b = (u32_a_t*)&pst;
-	for ( i=0; i< sizeof(pre)/sizeof(uint32_t); i++ ) {
-		a[i].u = 0xaffe0000 + i;
-	}
-	ppc_exc_set_handler(ASM_PROG_VECTOR, handle_clobber_exc);
-	clobber();
-	ppc_exc_set_handler(ASM_PROG_VECTOR, 0);
-	for ( i=0; i< sizeof(pre)/sizeof(uint32_t); i++ ) {
-		switch (i) {
-			case OFF(gpr1)/sizeof(uint32_t):
-			case OFF(gpr2)/sizeof(uint32_t):
-			case OFF(gpr13)/sizeof(uint32_t):
-			break;
-
-			default:
-				if ( a[i].u != b[i].u - 1  ) {
-					 printf("MISMATCH at %i: 0x%08"PRIx32" -- 0x%08"PRIx32"\n",
-					 	i, a[i].u, b[i].u);
-				}
-		}
-	}
-}
-
-#if 0
-void
-ppc_exc_test()
-{
-ppc_exc_int_regs a, b;
-int              i;
-	memset(&a, 0xaa, sizeof(a));
-	memset(&b, 0x55, sizeof(b));
-	storegs(&a, &b);
-	if ( memcmp(&a, &b, sizeof(a)) ) {
-		printf("FAILURE: context prior and after exception don't match!\n");
-	}
-	for ( i=0; i< sizeof(a)/sizeof(uint32_t); i++ ) {
-			printf("0x%08"PRIx32" -- 0x%08"PRIx32"\n",
-				((uint32_t __attribute__((may_alias)) *)&a)[i],
-				((uint32_t __attribute__((may_alias)) *)&b)[i]);
-	}
-}
-#endif
