Changeset fe7acdcf in rtems


Ignore:
Timestamp:
Jan 3, 2001, 4:36:23 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
d6ea098
Parents:
9fd4f5c5
Message:

2001-01-03 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Added _CPU_Initialize_vectors().
  • cpu_asm.S: Modify to properly dereference _ISR_Vector_table now that it is dynamically allocated.
Files:
24 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/h8300/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • c/src/exec/score/cpu/h8300/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    129129/* Vector to ISR */
    130130
    131         mov.l   #__ISR_Vector_table,er1
     131        mov.l   @__ISR_Vector_table,er1
    132132        mov             er0,er2 ; copy vector
    133133        shll.l  er2
  • c/src/exec/score/cpu/h8300/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    602602#define CPU_STACK_ALIGNMENT        2
    603603
    604 /* ISR handler macros */
     604/*
     605 *  ISR handler macros
     606 */
     607
     608/*
     609 *  Support routine to initialize the RTEMS vector table after it is allocated.
     610 */
     611
     612#define _CPU_Initialize_vectors()
    605613
    606614/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
  • c/src/exec/score/cpu/hppa1.1/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • c/src/exec/score/cpu/hppa1.1/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    312312        ldil      L%_ISR_Vector_table,%r8
    313313        ldo       R%_ISR_Vector_table(%r8),%r8
     314        ldw       (%r8),%r8
    314315        ldwx,s    %r9(%r8),%r8
    315316
  • c/src/exec/score/cpu/hppa1.1/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    339339 *
    340340 *  These macros perform the following functions:
     341 *     + initialize the RTEMS vector table
    341342 *     + disable all maskable CPU interrupts
    342343 *     + restore previous interrupt level (enable)
     
    345346 */
    346347
     348/*
     349 *  Support routine to initialize the RTEMS vector table after it is allocated.
     350 */
     351
     352#define _CPU_Initialize_vectors()
     353
    347354/* Disable interrupts; returning previous psw bits in _isr_level */
     355
    348356#define _CPU_ISR_Disable( _isr_level ) \
    349357  do { \
     
    354362
    355363/* Enable interrupts to previous level from _CPU_ISR_Disable
    356  * does not change 'level' */
     364 * does not change 'level'
     365 */
     366
    357367#define _CPU_ISR_Enable( _isr_level )  \
    358368  { \
  • c/src/exec/score/cpu/m68k/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-12-19      Joel Sherrill <joel@OARcorp.com>
    28
  • c/src/exec/score/cpu/m68k/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    178178#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
    179179
     180        movel   SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
    180181#if ( M68K_HAS_PREINDEXING == 1 )
    181         movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
    182 #else
    183         movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
     182        movel   (a0,d0:w:1),a0           | a0 = address of user routine
     183#else
    184184        addal   d0,a0                    | a0 = address of vector
    185185        movel   (a0),a0                  | a0 = address of user routine
  • c/src/exec/score/cpu/m68k/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    310310 *
    311311 *  These macros perform the following functions:
     312 *     + initialize the RTEMS vector table
    312313 *     + disable all maskable CPU interrupts
    313314 *     + restore previous interrupt level (enable)
     
    315316 *     + set a particular level
    316317 */
     318
     319#define _CPU_Initialize_vectors()
    317320
    318321#define _CPU_ISR_Disable( _level ) \
  • c/src/exec/score/cpu/sparc/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-12-06      Joel Sherrill <joel@OARcorp.com>
    28
  • c/src/exec/score/cpu/sparc/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    586586
    587587        sethi    %hi(SYM(_ISR_Vector_table)), %g4
    588         or       %g4, %lo(SYM(_ISR_Vector_table)), %g4
     588        ld       [%g4+%lo(SYM(_ISR_Vector_table))], %g4
    589589        and      %l3, 0xFF, %g5         ! remove synchronous trap indicator
    590590        sll      %g5, 2, %g5            ! g5 = offset into table
  • c/src/exec/score/cpu/sparc/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    719719extern void sparc_enable_interrupts();
    720720
    721 /* ISR handler macros */
     721/*
     722 *  ISR handler macros
     723 */
     724
     725/*
     726 *  Support routine to initialize the RTEMS vector table after it is allocated.
     727 */
     728
     729#define _CPU_Initialize_vectors()
    722730
    723731/*
  • cpukit/score/cpu/h8300/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • cpukit/score/cpu/h8300/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    129129/* Vector to ISR */
    130130
    131         mov.l   #__ISR_Vector_table,er1
     131        mov.l   @__ISR_Vector_table,er1
    132132        mov             er0,er2 ; copy vector
    133133        shll.l  er2
  • cpukit/score/cpu/h8300/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    602602#define CPU_STACK_ALIGNMENT        2
    603603
    604 /* ISR handler macros */
     604/*
     605 *  ISR handler macros
     606 */
     607
     608/*
     609 *  Support routine to initialize the RTEMS vector table after it is allocated.
     610 */
     611
     612#define _CPU_Initialize_vectors()
    605613
    606614/* COPE With Brain dead version of GCC distributed with Hitachi HIView Tools.
  • cpukit/score/cpu/hppa1.1/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    28
  • cpukit/score/cpu/hppa1.1/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    312312        ldil      L%_ISR_Vector_table,%r8
    313313        ldo       R%_ISR_Vector_table(%r8),%r8
     314        ldw       (%r8),%r8
    314315        ldwx,s    %r9(%r8),%r8
    315316
  • cpukit/score/cpu/hppa1.1/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    339339 *
    340340 *  These macros perform the following functions:
     341 *     + initialize the RTEMS vector table
    341342 *     + disable all maskable CPU interrupts
    342343 *     + restore previous interrupt level (enable)
     
    345346 */
    346347
     348/*
     349 *  Support routine to initialize the RTEMS vector table after it is allocated.
     350 */
     351
     352#define _CPU_Initialize_vectors()
     353
    347354/* Disable interrupts; returning previous psw bits in _isr_level */
     355
    348356#define _CPU_ISR_Disable( _isr_level ) \
    349357  do { \
     
    354362
    355363/* Enable interrupts to previous level from _CPU_ISR_Disable
    356  * does not change 'level' */
     364 * does not change 'level'
     365 */
     366
    357367#define _CPU_ISR_Enable( _isr_level )  \
    358368  { \
  • cpukit/score/cpu/m68k/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-12-19      Joel Sherrill <joel@OARcorp.com>
    28
  • cpukit/score/cpu/m68k/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    178178#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
    179179
     180        movel   SYM (_ISR_Vector_table),a0 | a0= base of RTEMS table
    180181#if ( M68K_HAS_PREINDEXING == 1 )
    181         movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
    182 #else
    183         movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
     182        movel   (a0,d0:w:1),a0           | a0 = address of user routine
     183#else
    184184        addal   d0,a0                    | a0 = address of vector
    185185        movel   (a0),a0                  | a0 = address of user routine
  • cpukit/score/cpu/m68k/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    310310 *
    311311 *  These macros perform the following functions:
     312 *     + initialize the RTEMS vector table
    312313 *     + disable all maskable CPU interrupts
    313314 *     + restore previous interrupt level (enable)
     
    315316 *     + set a particular level
    316317 */
     318
     319#define _CPU_Initialize_vectors()
    317320
    318321#define _CPU_ISR_Disable( _level ) \
  • cpukit/score/cpu/sparc/ChangeLog

    r9fd4f5c5 rfe7acdcf  
     12001-01-03      Joel Sherrill <joel@OARcorp.com>
     2
     3        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
     4        * cpu_asm.S: Modify to properly dereference _ISR_Vector_table
     5        now that it is dynamically allocated.
     6
    172000-12-06      Joel Sherrill <joel@OARcorp.com>
    28
  • cpukit/score/cpu/sparc/cpu_asm.S

    r9fd4f5c5 rfe7acdcf  
    586586
    587587        sethi    %hi(SYM(_ISR_Vector_table)), %g4
    588         or       %g4, %lo(SYM(_ISR_Vector_table)), %g4
     588        ld       [%g4+%lo(SYM(_ISR_Vector_table))], %g4
    589589        and      %l3, 0xFF, %g5         ! remove synchronous trap indicator
    590590        sll      %g5, 2, %g5            ! g5 = offset into table
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    r9fd4f5c5 rfe7acdcf  
    719719extern void sparc_enable_interrupts();
    720720
    721 /* ISR handler macros */
     721/*
     722 *  ISR handler macros
     723 */
     724
     725/*
     726 *  Support routine to initialize the RTEMS vector table after it is allocated.
     727 */
     728
     729#define _CPU_Initialize_vectors()
    722730
    723731/*
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