Changeset fe5d5048 in rtems


Ignore:
Timestamp:
Nov 12, 2010, 12:43:28 PM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
82dcbc8
Parents:
0badd509
Message:

2010-11-12 Sebastian Huber <sebastian.huber@…>

  • mpc55xx/include/irq.h: Include missing <bspopts.h>. Format.
  • mpc83xx/include/mpc83xx.h, mpc83xx/i2c/mpc83xx_i2cdrv.h, mpc83xx/i2c/mpc83xx_i2cdrv.c: Changes to use this driver for the MPC55XX familiy.
Location:
c/src/lib/libcpu/powerpc
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/ChangeLog

    r0badd509 rfe5d5048  
     12010-11-12      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * mpc55xx/include/irq.h: Include missing <bspopts.h>.  Format.
     4        * mpc83xx/include/mpc83xx.h, mpc83xx/i2c/mpc83xx_i2cdrv.h,
     5        mpc83xx/i2c/mpc83xx_i2cdrv.c: Changes to use this driver for the
     6        MPC55XX familiy.
     7
    182010-08-15      Joel Sherrill <joel.sherrilL@OARcorp.com>
    29
  • c/src/lib/libcpu/powerpc/mpc55xx/include/irq.h

    r0badd509 rfe5d5048  
    2525#include <rtems/irq.h>
    2626
     27#include <bspopts.h>
     28
    2729#ifdef __cplusplus
    2830extern "C" {
     
    4446#define MPC55XX_IRQ_SOFTWARE_MIN 0U
    4547#define MPC55XX_IRQ_SOFTWARE_MAX 7U
    46 #define MPC55XX_IRQ_SOFTWARE_GET_INDEX( v) (v)
    47 #define MPC55XX_IRQ_SOFTWARE_GET_REQUEST( i) (i)
     48#define MPC55XX_IRQ_SOFTWARE_GET_INDEX(v) (v)
     49#define MPC55XX_IRQ_SOFTWARE_GET_REQUEST(i) (i)
    4850#define MPC55XX_IRQ_SOFTWARE_NUMBER (MPC55XX_IRQ_SOFTWARE_MAX + 1U)
    4951
    50 #if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
    51 #else  /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
    52 #endif /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
     52#if MPC55XX_CHIP_TYPE >= 5510 && MPC55XX_CHIP_TYPE <= 5517
     53  /* eDMA interrupts */
     54  #define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
     55  #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
     56  #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 26U
    5357
    54 #if ((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))
     58  #define MPC55XX_IRQ_EDMA_GET_CHANNEL(v) \
     59    ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
     60  #define MPC55XX_IRQ_EDMA_GET_REQUEST(c) \
     61    ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
    5562
    56 /* eDMA interrupts */
    57 #define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
    58 #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
    59 #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 26U
     63  /* I2C interrupt */
     64  #define MPC55XX_IRQ_I2C 48U
    6065
    61 #define MPC55XX_IRQ_EDMA_GET_CHANNEL( v) \
    62   ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
    63 #define MPC55XX_IRQ_EDMA_GET_REQUEST( c) \
    64   ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN)
     66  /* SIU external interrupts */
     67  #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
     68  #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
     69  #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
     70  #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
     71  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
    6572
    66 /* SIU external interrupts */
    67 #define MPC55XX_IRQ_SIU_EXTERNAL_0 53U
    68 #define MPC55XX_IRQ_SIU_EXTERNAL_1 54U
    69 #define MPC55XX_IRQ_SIU_EXTERNAL_2 55U
    70 #define MPC55XX_IRQ_SIU_EXTERNAL_3 56U
    71 #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 57U
     73  /* eMIOS interrupts */
     74  #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 58U
     75  #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 81U
     76  #define MPC55XX_IRQ_EMIOS_GET_CHANNEL(v) \
     77    ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
     78  #define MPC55XX_IRQ_EMIOS_GET_REQUEST(c) \
     79    ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
     80#elif MPC55XX_CHIP_TYPE >= 5554 && MPC55XX_CHIP_TYPE <= 5567
     81  /* eDMA interrupts */
     82  #define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
     83  #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
     84  #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 42U
    7285
    73 /* eMIOS interrupts */
    74 #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 58U
    75 #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 81U
    76 #define MPC55XX_IRQ_EMIOS_GET_CHANNEL( v) \
    77   ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
    78 #define MPC55XX_IRQ_EMIOS_GET_REQUEST( c) \
    79   ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN)
     86  #define MPC55XX_IRQ_EDMA_ERROR_HIGH 210U
     87  #define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN 211U
     88  #define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MAX 242U
    8089
    81 #else  /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
     90  #define MPC55XX_IRQ_EDMA_GET_CHANNEL(v) \
     91    (((v) > MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX) \
     92      ? ((v) + 32U - MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) \
     93      : ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
     94  #define MPC55XX_IRQ_EDMA_GET_REQUEST(c) \
     95    (((c) >= 32U) \
     96      ? ((c) - 32U + MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) \
     97      : ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
    8298
    83 /* eDMA interrupts */
    84 #define MPC55XX_IRQ_EDMA_ERROR_LOW 10U
    85 #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN 11U
    86 #define MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX 42U
     99  /* SIU external interrupts */
     100  #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
     101  #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
     102  #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
     103  #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
     104  #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
    87105
    88 #define MPC55XX_IRQ_EDMA_ERROR_HIGH 210U
    89 #define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN 211U
    90 #define MPC55XX_IRQ_EDMA_REQUEST_HIGH_MAX 242U
     106  /* eMIOS interrupts */
     107  #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 51U
     108  #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 66U
     109  #define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN 202U
     110  #define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MAX 209U
    91111
    92 #define MPC55XX_IRQ_EDMA_GET_CHANNEL( v) \
    93   (((v) > MPC55XX_IRQ_EDMA_REQUEST_LOW_MAX)             \
    94    ? ((v) + 32U - MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN)    \
    95    : ((v) - MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
    96 #define MPC55XX_IRQ_EDMA_GET_REQUEST( c) \
    97   (((c) >= 32U)                                      \
    98    ? ((c) - 32U + MPC55XX_IRQ_EDMA_REQUEST_HIGH_MIN) \
    99    : ((c) + MPC55XX_IRQ_EDMA_REQUEST_LOW_MIN))
     112  #define MPC55XX_IRQ_EMIOS_GET_CHANNEL(v) \
     113    (((v) > MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX) \
     114      ? ((v) + 16U - MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
     115      : ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
    100116
    101 /* SIU external interrupts */
    102 #define MPC55XX_IRQ_SIU_EXTERNAL_0 46U
    103 #define MPC55XX_IRQ_SIU_EXTERNAL_1 47U
    104 #define MPC55XX_IRQ_SIU_EXTERNAL_2 48U
    105 #define MPC55XX_IRQ_SIU_EXTERNAL_3 49U
    106 #define MPC55XX_IRQ_SIU_EXTERNAL_4_15 50U
    107 
    108 /* eMIOS interrupts */
    109 #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN 51U
    110 #define MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX 66U
    111 #define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN 202U
    112 #define MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MAX 209U
    113 
    114 #define MPC55XX_IRQ_EMIOS_GET_CHANNEL( v)             \
    115   (((v) > MPC55XX_IRQ_EMIOS_REQUEST_LOW_MAX)          \
    116    ? ((v) + 16U - MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
    117    : ((v) - MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
    118 
    119 #define MPC55XX_IRQ_EMIOS_GET_REQUEST( c)             \
    120   (((c) >= 16U)                                       \
    121    ? ((c) - 16U + MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
    122    : ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
    123 
    124 #endif /*((MPC55XX_CHIP_TYPE >= 5510) && (MPC55XX_CHIP_TYPE <= 5517))*/
     117  #define MPC55XX_IRQ_EMIOS_GET_REQUEST(c) \
     118    (((c) >= 16U) \
     119      ? ((c) - 16U + MPC55XX_IRQ_EMIOS_REQUEST_HIGH_MIN) \
     120      : ((c) + MPC55XX_IRQ_EMIOS_REQUEST_LOW_MIN))
     121#else
     122  #error "unexpected chip type"
     123#endif
    125124
    126125/* Checks */
    127126#define MPC55XX_IRQ_IS_VALID(v) \
    128   ((v) >= MPC55XX_IRQ_MIN &&    \
     127  ((v) >= MPC55XX_IRQ_MIN && \
    129128   (v) <= MPC55XX_IRQ_MAX)
    130129#define MPC55XX_IRQ_IS_SOFTWARE(v) \
     
    141140#define MPC55XX_INTC_INVALID_PRIORITY (MPC55XX_INTC_MAX_PRIORITY + 1)
    142141#define MPC55XX_INTC_DEFAULT_PRIORITY (MPC55XX_INTC_MIN_PRIORITY + 1)
    143 #define MPC55XX_INTC_IS_VALID_PRIORITY(p) ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY)
     142#define MPC55XX_INTC_IS_VALID_PRIORITY(p) \
     143  ((p) >= MPC55XX_INTC_DISABLED_PRIORITY && (p) <= MPC55XX_INTC_MAX_PRIORITY)
    144144
    145145rtems_status_code mpc55xx_interrupt_handler_install(
    146         rtems_vector_number vector,
    147         const char *info,
    148         rtems_option options,
    149         unsigned priority,
    150         rtems_interrupt_handler handler,
    151         void *arg
     146  rtems_vector_number vector,
     147  const char *info,
     148  rtems_option options,
     149  unsigned priority,
     150  rtems_interrupt_handler handler,
     151  void *arg
    152152);
    153153
    154 rtems_status_code mpc55xx_intc_get_priority( rtems_vector_number vector, unsigned *priority);
     154rtems_status_code mpc55xx_intc_get_priority(
     155  rtems_vector_number vector,
     156  unsigned *priority
     157);
    155158
    156 rtems_status_code mpc55xx_intc_set_priority( rtems_vector_number vector, unsigned priority);
     159rtems_status_code mpc55xx_intc_set_priority(
     160  rtems_vector_number vector,
     161  unsigned priority
     162);
    157163
    158 rtems_status_code mpc55xx_intc_raise_software_irq( rtems_vector_number vector);
     164rtems_status_code mpc55xx_intc_raise_software_irq(rtems_vector_number vector);
    159165
    160 rtems_status_code mpc55xx_intc_clear_software_irq( rtems_vector_number vector);
     166rtems_status_code mpc55xx_intc_clear_software_irq(rtems_vector_number vector);
    161167
    162168/**
  • c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.c

    r0badd509 rfe5d5048  
    2020#include <bsp.h>
    2121#include <bsp/irq.h>
    22 #include <mpc83xx/mpc83xx.h>
    23 #include <mpc83xx/mpc83xx_i2cdrv.h>
     22#if defined(__GEN83xx_BSP_h)
     23  #include <mpc83xx/mpc83xx_i2cdrv.h>
     24#elif defined(LIBBSP_POWERPC_MPC55XXEVB_BSP_H)
     25  #include <bsp/mpc83xx_i2cdrv.h>
     26#endif
    2427#include <rtems/error.h>
    2528#include <rtems/bspIo.h>
     
    2831
    2932#undef DEBUG
     33
     34#if defined(__GEN83xx_BSP_h)
     35  #define I2CCR_MEN  (1 << 7)   /* module enable */
     36#elif defined(LIBBSP_POWERPC_MPC55XXEVB_BSP_H)
     37  #define I2CCR_MDIS (1 << 7)   /* module disable */
     38#endif
     39#define I2CCR_MIEN (1 << 6)     /* module interrupt enable */
     40#define I2CCR_MSTA (1 << 5)     /* 0->1 generates a start condiiton, 1->0 a stop */
     41#define I2CCR_MTX  (1 << 4)     /* 0 = receive mode, 1 = transmit mode           */
     42#define I2CCR_TXAK (1 << 3)     /* 0 = send ack 1 = send nak during receive      */
     43#define I2CCR_RSTA (1 << 2)     /* 1 = send repeated start condition             */
     44#define I2CCR_BCST (1 << 0)     /* 0 = disable 1 = enable broadcast accept       */
     45
     46#define I2CSR_MCF  (1 << 7)     /* data transfer (0=transfer in progres) */
     47#define I2CSR_MAAS (1 << 6)     /* addessed as slave   */
     48#define I2CSR_MBB  (1 << 5)     /* bus busy            */
     49#define I2CSR_MAL  (1 << 4)     /* arbitration lost    */
     50#define I2CSR_BCSTM (1 << 3)    /* broadcast match     */
     51#define I2CSR_SRW  (1 << 2)     /* slave read/write    */
     52#define I2CSR_MIF  (1 << 1)     /* module interrupt    */
     53#define I2CSR_RXAK (1 << 0)     /* receive acknowledge */
    3054
    3155/*=========================================================================*\
     
    5579    int fdr_val;
    5680  } dividers[] ={
     81#if defined(__GEN83xx_BSP_h)
    5782    {  256,0x20 }, {  288,0x21 }, {  320,0x22 }, {  352,0x23 },
    5883    {  384,0x00 }, {  416,0x01 }, {  448,0x25 }, {  480,0x02 },
     
    6893    {30720,0x1B }, {32768,0x3F }, {36864,0x1C }, {40960,0x1D },
    6994    {49152,0x1E }, {61440,0x1F }
     95#elif defined(LIBBSP_POWERPC_MPC55XXEVB_BSP_H)
     96    { 768, 0x31 }
     97#endif
    7098  };
    7199
     
    121149     * enable interrupt mask
    122150     */
    123     softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_MIEN;
     151    softc_ptr->reg_ptr->i2ccr |= I2CCR_MIEN;
    124152    rc = rtems_semaphore_obtain(softc_ptr->irq_sema_id,RTEMS_WAIT,100);
    125153    if (rc != RTEMS_SUCCESSFUL) {
     
    136164        return RTEMS_TIMEOUT;
    137165      }
    138     } while (!(softc_ptr->reg_ptr->i2csr & MPC83XX_I2CSR_MIF));
    139   }
    140   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MIEN;
     166    } while (!(softc_ptr->reg_ptr->i2csr & I2CSR_MIF));
     167  }
     168  softc_ptr->reg_ptr->i2ccr &= ~I2CCR_MIEN;
    141169
    142170  act_status = softc_ptr->reg_ptr->i2csr;
     
    176204   * clear IRQ flag
    177205   */
    178   softc_ptr->reg_ptr->i2csr &= ~MPC83XX_I2CSR_MIF;
     206  softc_ptr->reg_ptr->i2csr &= ~I2CSR_MIF;
    179207
    180208  /*
    181209   * disable interrupt mask
    182210   */
    183   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MIEN;
     211  softc_ptr->reg_ptr->i2ccr &= ~I2CCR_MIEN;
    184212  if (softc_ptr->initialized) {
    185213    rtems_semaphore_release(softc_ptr->irq_sema_id);
     
    345373   * set control register to module enable
    346374   */
    347   softc_ptr->reg_ptr->i2ccr = MPC83XX_I2CCR_MEN;
     375  #if defined(__GEN83xx_BSP_h)
     376    softc_ptr->reg_ptr->i2ccr = I2CCR_MEN;
     377  #elif defined(LIBBSP_POWERPC_MPC55XXEVB_BSP_H)
     378    softc_ptr->reg_ptr->i2ccr = 0;
     379  #endif
    348380
    349381  /*
     
    385417  printk("mpc83xx_i2c_send_start called... ");
    386418#endif
    387   if (0 != (softc_ptr->reg_ptr->i2ccr & MPC83XX_I2CCR_MSTA)) {
     419  if (0 != (softc_ptr->reg_ptr->i2ccr & I2CCR_MSTA)) {
    388420    /*
    389421     * already started, so send a "repeated start"
    390422     */
    391     softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_RSTA;
     423    softc_ptr->reg_ptr->i2ccr |= I2CCR_RSTA;
    392424  }
    393425  else {
    394     softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_MSTA;
     426    softc_ptr->reg_ptr->i2ccr |= I2CCR_MSTA;
    395427  }
    396428
     
    424456  printk("mpc83xx_i2c_send_stop called... ");
    425457#endif
    426   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MSTA;
     458  softc_ptr->reg_ptr->i2ccr &= ~I2CCR_MSTA;
    427459  /*
    428460   * wait, 'til stop has been executed
    429461   */
    430   while (0 != (softc_ptr->reg_ptr->i2csr & MPC83XX_I2CSR_MBB)) {
     462  while (0 != (softc_ptr->reg_ptr->i2csr & I2CSR_MBB)) {
    431463    rtems_task_wake_after(RTEMS_YIELD_PROCESSOR);
    432464  }
     
    465497  printk("mpc83xx_i2c_send_addr called... ");
    466498#endif
    467   softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_MTX;
     499  softc_ptr->reg_ptr->i2ccr |= I2CCR_MTX;
    468500  /*
    469501   * determine, whether short or long address is needed, determine rd/wr
     
    481513     * wait for successful transfer
    482514     */
    483     rc = mpc83xx_i2c_wait(softc_ptr,
    484                           MPC83XX_I2CSR_MCF,
    485                           MPC83XX_I2CSR_MCF);
     515    rc = mpc83xx_i2c_wait(softc_ptr, I2CSR_MCF, I2CSR_MCF | I2CSR_RXAK);
    486516    if (rc != RTEMS_SUCCESSFUL) {
    487517#if defined(DEBUG)
     
    501531   * wait for successful transfer
    502532   */
    503   rc = mpc83xx_i2c_wait(softc_ptr,
    504                         MPC83XX_I2CSR_MCF,
    505                         MPC83XX_I2CSR_MCF);
     533  rc = mpc83xx_i2c_wait(softc_ptr, I2CSR_MCF, I2CSR_MCF | I2CSR_RXAK);
    506534
    507535#if defined(DEBUG)
     
    539567  printk("mpc83xx_i2c_read_bytes called... ");
    540568#endif
    541   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_MTX;
    542   softc_ptr->reg_ptr->i2ccr &= ~MPC83XX_I2CCR_TXAK;
     569  softc_ptr->reg_ptr->i2ccr &= ~I2CCR_MTX;
     570  softc_ptr->reg_ptr->i2ccr &= ~I2CCR_TXAK;
    543571  /*
    544572   * FIXME: do we need to deactivate TXAK from the start,
     
    555583       * last byte is not acknowledged
    556584       */
    557       softc_ptr->reg_ptr->i2ccr |= MPC83XX_I2CCR_TXAK;
     585      softc_ptr->reg_ptr->i2ccr |= I2CCR_TXAK;
    558586    }
    559587    /*
    560588     * wait 'til end of transfer
    561589     */
    562     rc = mpc83xx_i2c_wait(softc_ptr,
    563                           MPC83XX_I2CSR_MCF,
    564                           MPC83XX_I2CSR_MCF);
     590    rc = mpc83xx_i2c_wait(softc_ptr, I2CSR_MCF, I2CSR_MCF);
    565591    if (rc != RTEMS_SUCCESSFUL) {
    566592#if defined(DEBUG)
     
    576602  * wait 'til end of last transfer
    577603  */
    578   rc = mpc83xx_i2c_wait(softc_ptr, MPC83XX_I2CSR_MCF, MPC83XX_I2CSR_MCF);
     604  rc = mpc83xx_i2c_wait(softc_ptr, I2CSR_MCF, I2CSR_MCF);
    579605
    580606#if defined(DEBUG)
     
    613639#endif
    614640  softc_ptr->reg_ptr->i2ccr =
    615     (softc_ptr->reg_ptr->i2ccr & ~MPC83XX_I2CCR_TXAK) | MPC83XX_I2CCR_MTX;
     641    (softc_ptr->reg_ptr->i2ccr & ~I2CCR_TXAK) | I2CCR_MTX;
    616642  while (len-- > 0) {
     643    int rxack = len != 0 ? I2CSR_RXAK : 0;
     644
    617645    softc_ptr->reg_ptr->i2cdr = *p++;
    618646    /*
    619647     * wait 'til end of transfer
    620648     */
    621     rc = mpc83xx_i2c_wait(softc_ptr,
    622                           MPC83XX_I2CSR_MCF,
    623                           MPC83XX_I2CSR_MCF);
     649    rc = mpc83xx_i2c_wait(softc_ptr, I2CSR_MCF, I2CSR_MCF | rxack);
    624650    if (rc != RTEMS_SUCCESSFUL) {
    625651#if defined(DEBUG)
  • c/src/lib/libcpu/powerpc/mpc83xx/i2c/mpc83xx_i2cdrv.h

    r0badd509 rfe5d5048  
    2020#define _MPC83XX_I2CDRV_H
    2121
    22 #include <mpc83xx/mpc83xx.h>
    2322#include <rtems/libi2c.h>
    2423#include <rtems/irq.h>
    2524
     25#include <bsp.h>
     26
     27#ifdef __GEN83xx_BSP_h
     28  #include <mpc83xx/mpc83xx.h>
     29#endif
     30
    2631#ifdef __cplusplus
    2732extern "C" {
     33#endif
     34
     35#ifdef LIBBSP_POWERPC_MPC55XXEVB_BSP_H
     36  typedef struct {
     37    volatile uint8_t i2cadr;
     38    volatile uint8_t i2cfdr;
     39    volatile uint8_t i2ccr;
     40    volatile uint8_t i2csr;
     41    volatile uint8_t i2cdr;
     42    volatile uint8_t i2cdfsrr;
     43  } m83xxI2CRegisters_t;
    2844#endif
    2945
  • c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h

    r0badd509 rfe5d5048  
    295295  uint8_t reserved0_3018[0x03100-0x03018]; /* 0x0_3018-30FF Reserved, should be cleared */
    296296} m83xxI2CRegisters_t;
    297 
    298 #define  MPC83XX_I2CCR_MEN  (1 << 7)     /* module enable */
    299 #define  MPC83XX_I2CCR_MIEN (1 << 6)     /* module interrupt enable */
    300 #define  MPC83XX_I2CCR_MSTA (1 << 5)     /* 0->1 generates a start condiiton, 1->0 a stop */
    301 #define  MPC83XX_I2CCR_MTX  (1 << 4)     /* 0 = receive mode, 1 = transmit mode           */
    302 #define  MPC83XX_I2CCR_TXAK (1 << 3)     /* 0 = send ack 1 = send nak during receive      */
    303 #define  MPC83XX_I2CCR_RSTA (1 << 2)     /* 1 = send repeated start condition             */
    304 #define  MPC83XX_I2CCR_BCST (1 << 0)     /* 0 = disable 1 = enable broadcast accept       */
    305 
    306 #define  MPC83XX_I2CSR_MCF  (1 << 7)     /* data transfer (0=transfer in progres) */
    307 #define  MPC83XX_I2CSR_MAAS (1 << 6)     /* addessed as slave   */
    308 #define  MPC83XX_I2CSR_MBB  (1 << 5)     /* bus busy            */
    309 #define  MPC83XX_I2CSR_MAL  (1 << 4)     /* arbitration lost    */
    310 #define  MPC83XX_I2CSR_BCSTM (1 << 3)    /* broadcast match     */
    311 #define  MPC83XX_I2CSR_SRW  (1 << 2)     /* slave read/write    */
    312 #define  MPC83XX_I2CSR_MIF  (1 << 1)     /* module interrupt    */
    313 #define  MPC83XX_I2CSR_RXAK (1 << 0)     /* receive acknowledge */
    314 
    315297
    316298  /* DUART */
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