Changeset fda47cd in rtems


Ignore:
Timestamp:
Oct 24, 2000, 9:48:33 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
86748ff
Parents:
6bb5260
Message:

2000-10-24 Alan Cudmore <alanc@…> and

Joel Sherrill <joel@…>

  • This is a major reworking of the mips64orion port to use gcc predefines as much as possible and a big push to multilib the mips port. The mips64orion port was copied/renamed to mips to be more like other GNU tools. Alan did most of the technical work of determining how to map old macro names used by the mips64orion port to standard compiler macro definitions. Joel did the merge with CVS magic to keep individual file history and did the BSP modifications. Details follow:
  • Makefile.am: idtmon.h in mips64orion port not present.
  • asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
  • cpu.c: Comments added.
  • cpu_asm.S: Conditionals changed. MIPS ISA level 1 support added. First attempt at exception/interrupt processing for ISA level 1 and minus any use of IDT/MON added.
  • idtcpu.h: Conditionals changed to use gcc predefines.
  • iregdef.h: Ditto.
  • cpu_asm.h: No real change. Merger required commit.
  • rtems/Makefile.am: Ditto.
  • rtems/score/Makefile.am: Ditto.
  • rtems/score/cpu.h: Change MIPS64ORION to MIPS.
  • rtems/score/mips64orion.h: Change MIPS64ORION to MIPS. Convert from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
Files:
1 deleted
24 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    r6bb5260 rfda47cd  
     12000-10-24      Alan Cudmore <alanc@linuxstart.com> and
     2        Joel Sherrill <joel@OARcorp.com>
     3
     4        * This is a major reworking of the mips64orion port to use
     5        gcc predefines as much as possible and a big push to multilib
     6        the mips port.  The mips64orion port was copied/renamed to mips
     7        to be more like other GNU tools.  Alan did most of the technical
     8        work of determining how to map old macro names used by the mips64orion
     9        port to standard compiler macro definitions.  Joel did the merge
     10        with CVS magic to keep individual file history and did the BSP
     11        modifications. Details follow:
     12        * Makefile.am: idtmon.h in mips64orion port not present.
     13        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
     14        * cpu.c: Comments added.
     15        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
     16        First attempt at exception/interrupt processing for ISA level 1
     17        and minus any use of IDT/MON added.
     18        * idtcpu.h: Conditionals changed to use gcc predefines.
     19        * iregdef.h: Ditto.
     20        * cpu_asm.h: No real change.  Merger required commit.
     21        * rtems/Makefile.am: Ditto.
     22        * rtems/score/Makefile.am: Ditto.
     23        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
     24        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
     25        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
     26
    1272000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    228
  • c/src/exec/score/cpu/mips/Makefile.am

    r6bb5260 rfda47cd  
    1111C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
    1212
    13 H_FILES = asm.h cpu_asm.h idtcpu.h idtmon.h iregdef.h
     13H_FILES = asm.h cpu_asm.h idtcpu.h iregdef.h
    1414
    1515S_FILES = cpu_asm.S
     
    4545.PRECIOUS: $(REL)
    4646
    47 EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h idtmon.h iregdef.h \
     47EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h iregdef.h \
    4848    rtems.c
    4949
  • c/src/exec/score/cpu/mips/asm.h

    r6bb5260 rfda47cd  
    2525/* @(#)asm.h       03/15/96     1.1 */
    2626
    27 #ifndef __MIPS64ORION_ASM_h
    28 #define __MIPS64ORION_ASM_h
     27#ifndef __NO_CPU_ASM_h
     28#define __NO_CPU_ASM_h
    2929
    3030/*
     
    9797#define EXTERN(sym) .globl SYM (sym)
    9898
     99/*
     100 *  Debugger macros for assembly language routines. Allows the
     101 *  programmer to set up the necessary stack frame info
     102 *  required by debuggers to do stack traces.
     103 */
     104
     105#ifndef XDS
     106#define FRAME(name,frm_reg,offset,ret_reg)      \
     107        .globl  name;                           \
     108        .ent    name;                           \
     109name:;                                          \
     110        .frame  frm_reg,offset,ret_reg
     111#define ENDFRAME(name)                          \
     112        .end name
     113#else
     114#define FRAME(name,frm_reg,offset,ret_reg)      \
     115        .globl  _##name;\
     116_##name:
     117#define ENDFRAME(name)
     118#endif  XDS
     119
    99120#endif
    100121/* end of include file */
    101122
    102 
  • c/src/exec/score/cpu/mips/configure.in

    r6bb5260 rfda47cd  
    1010RTEMS_CANONICAL_TARGET_CPU
    1111
    12 AM_INIT_AUTOMAKE(rtems-c-src-exec-score-cpu-mips64orion,$RTEMS_VERSION,no)
     12AM_INIT_AUTOMAKE(rtems-c-src-exec-score-cpu-mips,$RTEMS_VERSION,no)
    1313AM_MAINTAINER_MODE
    1414
    15 RTEMS_ENV_RTEMSCPU
     15RTEMS_ENV_RTEMSBSP
    1616
    1717RTEMS_CHECK_CPU
     
    2525RTEMS_CHECK_NEWLIB
    2626
     27# Check if there is custom/*.cfg for this BSP
     28RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP)
     29
    2730# Explicitly list all Makefiles here
    2831AC_OUTPUT(
  • c/src/exec/score/cpu/mips/cpu.c

    r6bb5260 rfda47cd  
    22 *  Mips CPU Dependent Source
    33 *
    4  *  Author:     Craig Lebakken <craigl@transition.com>
    5  *
    6  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    7  *
    8  *  To anyone who acknowledges that this file is provided "AS IS"
    9  *  without any express or implied warranty:
    10  *      permission to use, copy, modify, and distribute this file
    11  *      for any purpose is hereby granted without fee, provided that
    12  *      the above copyright notice and this notice appears in all
    13  *      copies, and that the name of Transition Networks not be used in
    14  *      advertising or publicity pertaining to distribution of the
    15  *      software without specific, written prior permission.
    16  *      Transition Networks makes no representations about the suitability
    17  *      of this software for any purpose.
    18  *
    19  *  Derived from source copyrighted as follows:
     4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
     5 *           Joel Sherrill <joel@OARcorp.com>.
     6 *
     7 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
     8 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
     9 *
     10 *         To anyone who acknowledges that this file is provided "AS IS"
     11 *         without any express or implied warranty:
     12 *             permission to use, copy, modify, and distribute this file
     13 *             for any purpose is hereby granted without fee, provided that
     14 *             the above copyright notice and this notice appears in all
     15 *             copies, and that the name of Transition Networks not be used in
     16 *             advertising or publicity pertaining to distribution of the
     17 *             software without specific, written prior permission.
     18 *             Transition Networks makes no representations about the
     19 *             suitability of this software for any purpose.
     20 *
     21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
    2022 *
    2123 *  COPYRIGHT (c) 1989-1999.
     
    125127   *  table used by the CPU to dispatch interrupt handlers.
    126128   */
    127 
     129/* Q: This will become necessary for Non IDT/Sim use...*/
    128130#if 0 /* not necessary */
    129131/* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
  • c/src/exec/score/cpu/mips/cpu_asm.S

    r6bb5260 rfda47cd  
    2020 *      of this software for any purpose.
    2121 *
    22  *  Derived from source copyrighted as follows:
     22 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
    2323 *
    2424 *  COPYRIGHT (c) 1989-1999.
     
    4646        .end name
    4747
    48 
    4948#define EXCP_STACK_SIZE (NREGS*R_SZ)
    50 
    51 #if __ghs__
    52 #define sd sw
    53 #define ld lw
    54 #define dmtc0 mtc0
    55 #define dsll sll
    56 #define dmfc0 mfc0
    57 #endif
     49#define ISR_VEC_SIZE 4
    5850
    5951#if 1  /* 32 bit unsigned32 types */
     
    142134}
    143135#endif
     136
     137#if __mips == 3
    144138/* return the current exception level for the 4650 */
    145139FRAME(_CPU_ISR_Get_level,sp,0,ra)
     
    164158        bnez a0,_CPU_ISR_Set_2
    165159        nop
    166         nop
    167         mfc0 t0,C0_SR
     160        nop
     161        mfc0 t0, C0_SR
    168162        nop
    169163        li t1,~SR_EXL
     
    183177        mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
    184178        nop
    185         ori t0,SR_EXL|SR_IE             /* enable exception level  */
     179        ori  t0, SR_EXL|SR_IE           /* enable exception level */   
    186180        nop
    187181        mtc0 t0,C0_SR         
     
    191185        nop
    192186ENDFRAME(_CPU_ISR_Set_level)
     187
     188#elif __mips == 1
     189
     190/* MIPS ISA 1 ( R3000 ) */
     191/* These routines might not be needed for the R3000 */
     192/* Q:Who calls _CPU_ISR_Get/Set_level? */
     193FRAME(_CPU_ISR_Get_level,sp,0,ra)
     194        mfc0 v0,C0_SR
     195        nop
     196        andi v0, SR_IEC
     197        j ra
     198ENDFRAME(_CPU_ISR_Get_level)
     199
     200FRAME(_CPU_ISR_Set_level,sp,0,ra)
     201        nop
     202        mfc0 t0,C0_SR
     203        andi a0, SR_IEC
     204        or   t0, a0
     205        mtc0 t0,C0_SR
     206        nop
     207        j ra
     208ENDFRAME(_CPU_ISR_Set_level)
     209
     210#else
     211   #error "__mips is set to 1 or 3"
     212#endif
    193213
    194214/*
     
    324344 * }
    325345 */
     346#if __mips == 3
     347/* MIPS ISA Level 3 ( R4xxx ) */
    326348
    327349FRAME(_CPU_Context_switch,sp,0,ra)
     
    338360        sd sp,SP_OFFSET*8(a0)
    339361        sd fp,FP_OFFSET*8(a0)
    340         sd s0,S0_OFFSET*8(a0)
    341362        sd s1,S1_OFFSET*8(a0)
    342363        sd s2,S2_OFFSET*8(a0)
     
    376397ENDFRAME(_CPU_Context_switch)
    377398
     399#elif __mips == 1
     400/* MIPS ISA Level 1 ( R3000 ) */
     401
     402FRAME(_CPU_Context_switch,sp,0,ra)
     403
     404        mfc0 t0,C0_SR
     405        li t1,~SR_IEC
     406        sw t0,C0_SR_OFFSET*4(a0)        /* save status register */
     407        and t0,t1
     408        mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
     409
     410        sw ra,RA_OFFSET*4(a0)           /* save current context */
     411        sw sp,SP_OFFSET*4(a0)
     412        sw fp,FP_OFFSET*4(a0)
     413        sw s0,S0_OFFSET*4(a0)
     414        sw s1,S1_OFFSET*4(a0)
     415        sw s2,S2_OFFSET*4(a0)
     416        sw s3,S3_OFFSET*4(a0)
     417        sw s4,S4_OFFSET*4(a0)
     418        sw s5,S5_OFFSET*4(a0)
     419        sw s6,S6_OFFSET*4(a0)
     420        sw s7,S7_OFFSET*4(a0)
     421
     422        mfc0 t0,C0_EPC
     423        sw t0,C0_EPC_OFFSET*4(a0)
     424
     425_CPU_Context_switch_restore:
     426        lw s0,S0_OFFSET*4(a1)           /* restore context */
     427        lw s1,S1_OFFSET*4(a1)
     428        lw s2,S2_OFFSET*4(a1)
     429        lw s3,S3_OFFSET*4(a1)
     430        lw s4,S4_OFFSET*4(a1)
     431        lw s5,S5_OFFSET*4(a1)
     432        lw s6,S6_OFFSET*4(a1)
     433        lw s7,S7_OFFSET*4(a1)
     434        lw fp,FP_OFFSET*4(a1)
     435        lw sp,SP_OFFSET*4(a1)
     436        lw ra,RA_OFFSET*4(a1)
     437        lw t0,C0_EPC_OFFSET*4(a1)
     438        mtc0 t0,C0_EPC
     439        lw t1, C0_SR_OFFSET*4(a1)
     440        mtc0 t1,C0_SR
     441
     442        /* Q:Changes needed to SR_IEC bit in SR/_CPU_Context_switch_restore? */
     443
     444_CPU_Context_1:
     445        j ra
     446        nop
     447ENDFRAME(_CPU_Context_switch)
     448
     449#else
     450
     451   #error "__mips is not set to 1 or 3"
     452
     453#endif
     454
    378455/*
    379456 *  _CPU_Context_restore
     
    393470#endif
    394471
     472#if __mips == 3
     473
    395474FRAME(_CPU_Context_restore,sp,0,ra)
    396475        dadd a1,a0,zero
     
    398477        nop
    399478ENDFRAME(_CPU_Context_restore)
     479
     480#elif __mips == 1
     481
     482FRAME(_CPU_Context_restore,sp,0,ra)
     483        add  a1,a0,zero
     484        j _CPU_Ccontext_switch_restore
     485        nop
     486ENDFRAME(_CPU_Context_restore)
     487
     488#else
     489
     490      #error "__mips is not set to 1 or 3"
     491
     492#endif
    400493
    401494EXTERN(_ISR_Nest_level, SZ_INT)
     
    439532   */
    440533#endif
     534
     535#if __mips == 3
     536/* ----------------------------------------------------------------------------- */
    441537FRAME(_ISR_Handler,sp,0,ra)
    442538.set noreorder
     
    488584        mfc0 k0,C0_CAUSE
    489585        and k1,k0,CAUSE_EXCMASK
    490         bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */
    491         mfc0 k1,C0_SR
     586        bnez k1,_ISR_Handler_prom_exit /* not an external interrup
     587t, pass exception to Monitor */
     588        mfc0 k1,C0_SR
    492589        and k0,k1
    493590        and k0,CAUSE_IPMASK
     
    662759
    663760_ISR_Handler_prom_exit:
    664 #ifdef CPU_R3000
     761#if __mips == 1
    665762        la      k0, (R_VEC+((48)*8))
    666763#endif
    667764
    668 #ifdef CPU_R4000
     765#if __mips == 3
    669766        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    670767#endif
     
    676773ENDFRAME(_ISR_Handler)
    677774
     775/* ---------------------------------------------------------------------- */
     776#elif __mips == 1
     777/* MIPS ISA Level 1 */
     778
     779FRAME(_ISR_Handler,sp,0,ra)
     780.set noreorder
     781
     782        /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */
     783
     784        addiu sp,sp,-EXCP_STACK_SIZE       /* wastes alot of stack space for context?? */
     785
     786        sw    ra, R_RA*R_SZ(sp)  /* store ra on the stack */
     787        sw    v0, R_V0*R_SZ(sp)
     788        sw    v1, R_V1*R_SZ(sp)
     789        sw    a0, R_A0*R_SZ(sp)
     790        sw    a1, R_A1*R_SZ(sp)
     791        sw    a2, R_A2*R_SZ(sp)
     792        sw    a3, R_A3*R_SZ(sp)
     793        sw    t0, R_T0*R_SZ(sp)
     794        sw    t1, R_T1*R_SZ(sp)
     795        sw    t2, R_T2*R_SZ(sp)
     796        sw    t3, R_T3*R_SZ(sp)
     797        sw    t4, R_T4*R_SZ(sp)
     798        sw    t5, R_T5*R_SZ(sp)
     799        sw    t6, R_T6*R_SZ(sp)
     800        sw    t7, R_T7*R_SZ(sp)
     801        mflo    k0
     802        sw    t8, R_T8*R_SZ(sp)
     803        sw    k0, R_MDLO*R_SZ(sp)
     804        sw    t9, R_T9*R_SZ(sp)
     805        mfhi    k0
     806        sw    gp, R_GP*R_SZ(sp)
     807        sw    fp, R_FP*R_SZ(sp)
     808        sw    k0, R_MDHI*R_SZ(sp)
     809        .set noat
     810        sw    AT, R_AT*R_SZ(sp)
     811        .set at
     812
     813        /* Q: Why hardcode -40 for stack add??? */
     814        /* This needs to be figured out.........*/
     815        addiu sp,sp,-40
     816        sw ra,32(sp)    /* store ra on the stack */
     817
     818/* determine if an interrupt generated this exception */
     819
     820        mfc0 k0,C0_CAUSE
     821        and k1,k0,CAUSE_EXCMASK
     822        beq k1, 0, _ISR_Handler_1
     823        nop
     824
     825_ISR_Handler_Exception:
     826        nop
     827        b  _ISR_Handler_Exception       /* Jump to the exception code */
     828        nop
     829
     830_ISR_Handler_1:
     831
     832        mfc0 k1,C0_SR
     833        and k0,k1
     834        and k0,CAUSE_IPMASK
     835        beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */
     836                                      /* but if it's not an exception or an interrupt,
     837                                      /* Then where did it come from??? */
     838        nop
     839
     840  /*
     841   *  save some or all context on stack
     842   *  may need to save some special interrupt information for exit
     843   *
     844   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
     845   *    if ( _ISR_Nest_level == 0 )
     846   *      switch to software interrupt stack
     847   *  #endif
     848   */
     849
     850  /*
     851   *  _ISR_Nest_level++;
     852   */
     853        lw   t0,_ISR_Nest_level
     854        addi t0,t0,1
     855        sw   t0,_ISR_Nest_level
     856  /*
     857   *  _Thread_Dispatch_disable_level++;
     858   */
     859        lw   t1,_Thread_Dispatch_disable_level
     860        addi t1,t1,1
     861        sw   t1,_Thread_Dispatch_disable_level
     862
     863  /*
     864   *  while ( interrupts_pending(cause_reg) ) {
     865   *     vector = BITFIELD_TO_INDEX(cause_reg);
     866   *     (*_ISR_Vector_table[ vector ])( vector );
     867   *  }
     868   */
     869        /* k0 has the SR interrupt bits */
     870        la t3, _ISR_vector_table
     871
     872        /* The bits you look at can be prioritized here just by */
     873        /*  changing what bit is looked at. I.E. SR_IBITx */
     874        /* This code might become a loop, servicing all ints before returning.. */
     875        /*   Right now, it will go thru the whole list once */
     876
     877_ISR_check_bit_0:
     878        and k1, k0, SR_IBIT1
     879        beq k1, zero, _ISR_check_bit_1
     880        nop
     881        li  t1, ISR_VEC_SIZE*0
     882        add t3, t1
     883        jal t3 
     884        nop
     885_ISR_check_bit_1:
     886        and k1, k0, SR_IBIT2
     887        beq k1, zero, _ISR_check_bit_2
     888        nop
     889        li  t1, ISR_VEC_SIZE*1
     890        add t3, t1
     891        jal t3
     892        nop
     893_ISR_check_bit_2:
     894        and k1, k0, SR_IBIT3
     895        beq k1, zero, _ISR_check_bit_3
     896        nop
     897        li  t1, ISR_VEC_SIZE*2
     898        add t3, t1
     899        jal t3
     900        nop
     901_ISR_check_bit_3:
     902        and k1, k0, SR_IBIT4
     903        beq k1, zero, _ISR_check_bit_4
     904        nop
     905        li  t1, ISR_VEC_SIZE*3
     906        add t3, t1
     907        jal t3
     908        nop
     909_ISR_check_bit_4:
     910        and k1, k0, SR_IBIT5
     911        beq k1, zero, _ISR_check_bit_5
     912        nop
     913        li  t1, ISR_VEC_SIZE*4
     914        add t3, t1
     915        jal t3
     916        nop
     917_ISR_check_bit_5:
     918        and k1, k0, SR_IBIT6
     919        beq k1, zero, _ISR_check_bit_6
     920        nop
     921        li  t1, ISR_VEC_SIZE*5
     922        add t3, t1
     923        jal t3
     924        nop
     925_ISR_check_bit_6:
     926        and k1, k0, SR_IBIT7
     927        beq k1, zero, _ISR_check_bit_7
     928        nop
     929        li  t1, ISR_VEC_SIZE*6
     930        add t3, t1
     931        jal t3
     932        nop
     933_ISR_check_bit_7:
     934        and k1, k0, SR_IBIT8
     935        beq k1, zero, _ISR_exit_int_check
     936        nop
     937        li  t1, ISR_VEC_SIZE*7
     938        add t3, t1
     939        jal t3
     940        nop
     941
     942_ISR_exit_int_check:
     943
     944  /*
     945   *  --_ISR_Nest_level;
     946   */
     947        lw   t2,_ISR_Nest_level
     948        addi t2,t2,-1
     949        sw   t2,_ISR_Nest_level
     950  /*
     951   *  --_Thread_Dispatch_disable_level;
     952   */
     953        lw   t1,_Thread_Dispatch_disable_level
     954        addi t1,t1,-1
     955        sw   t1,_Thread_Dispatch_disable_level
     956  /*
     957   *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
     958   *    goto the label "exit interrupt (simple case)"
     959   */
     960        or  t0,t2,t1
     961        bne t0,zero,_ISR_Handler_exit
     962        nop
     963  /*
     964   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
     965   *    restore stack
     966   *  #endif
     967   * 
     968   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
     969   *    goto the label "exit interrupt (simple case)"
     970   */
     971        lw  t0,_Context_Switch_necessary
     972        lw  t1,_ISR_Signals_to_thread_executing
     973        or  t0,t0,t1
     974        beq t0,zero,_ISR_Handler_exit
     975        nop
     976  /*
     977   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
     978   */
     979        jal _Thread_Dispatch
     980        nop
     981  /*
     982   *  prepare to get out of interrupt
     983   *  return from interrupt  (maybe to _ISR_Dispatch)
     984   *
     985   *  LABEL "exit interrupt (simple case):
     986   *  prepare to get out of interrupt
     987   *  return from interrupt
     988   */
     989
     990_ISR_Handler_exit:
     991        ld ra,32(sp)
     992        addiu sp,sp,40    /* Q: Again with the 40...Is this needed? */
     993
     994/* restore interrupt context from stack */
     995     
     996        lw    k0, R_MDLO*R_SZ(sp)           
     997        mtlo  k0
     998        lw    k0, R_MDHI*R_SZ(sp)           
     999        lw    a2, R_A2*R_SZ(sp)
     1000        mthi  k0
     1001        lw    a3, R_A3*R_SZ(sp)
     1002        lw    t0, R_T0*R_SZ(sp)
     1003        lw    t1, R_T1*R_SZ(sp)
     1004        lw    t2, R_T2*R_SZ(sp)
     1005        lw    t3, R_T3*R_SZ(sp)
     1006        lw    t4, R_T4*R_SZ(sp)
     1007        lw    t5, R_T5*R_SZ(sp)
     1008        lw    t6, R_T6*R_SZ(sp)
     1009        lw    t7, R_T7*R_SZ(sp)
     1010        lw    t8, R_T8*R_SZ(sp)
     1011        lw    t9, R_T9*R_SZ(sp)
     1012        lw    gp, R_GP*R_SZ(sp)
     1013        lw    fp, R_FP*R_SZ(sp)
     1014        lw    ra, R_RA*R_SZ(sp)
     1015        lw    a0, R_A0*R_SZ(sp)
     1016        lw    a1, R_A1*R_SZ(sp)
     1017        lw    v1, R_V1*R_SZ(sp)
     1018        lw    v0, R_V0*R_SZ(sp)
     1019        .set noat
     1020        lw    AT, R_AT*R_SZ(sp)
     1021        .set at
     1022
     1023        addiu sp,sp,EXCP_STACK_SIZE
     1024       
     1025        rfe  /* Might not need to do RFE here... */
     1026        j ra
     1027        nop
     1028
     1029       .set    reorder
     1030ENDFRAME(_ISR_Handler)
     1031
     1032#else
     1033
     1034   #error "__mips is not set to 1 or 3 "
     1035
     1036#endif
    6781037
    6791038FRAME(mips_enable_interrupts,sp,0,ra)
     
    6971056ENDFRAME(mips_disable_interrupts)
    6981057
     1058#if __mips == 3
     1059
    6991060FRAME(mips_enable_global_interrupts,sp,0,ra)
    7001061        mfc0 t0,C0_SR           /* get status reg */
     
    7161077ENDFRAME(mips_disable_global_interrupts)
    7171078
     1079#elif __mips == 1
     1080
     1081FRAME(mips_enable_global_interrupts,sp,0,ra)
     1082        mfc0 t0,C0_SR           /* get status reg */
     1083        nop
     1084        ori t0,SR_IEC
     1085        mtc0 t0,C0_SR           /* save updated status reg */
     1086        j ra
     1087        nop
     1088ENDFRAME(mips_enable_global_interrupts)
     1089
     1090FRAME(mips_disable_global_interrupts,sp,0,ra)
     1091        li t1,SR_IEC
     1092        mfc0 t0,C0_SR           /* get status reg */
     1093        not t1
     1094        and t0,t1
     1095        mtc0 t0,C0_SR           /* save updated status reg */
     1096        j ra
     1097        nop
     1098ENDFRAME(mips_disable_global_interrupts)
     1099
     1100#else
     1101
     1102   #error "__mips is not set to 1 or 3"
     1103
     1104#endif
     1105
    7181106/* return the value of the status register in v0.  Used for debugging */
    7191107FRAME(mips_get_sr,sp,0,ra)
     
    7331121ENDFRAME(mips_break)
    7341122
     1123
     1124/**************************************************************************
     1125**
     1126** enable_int(mask) - enables interrupts - mask is positioned so it only
     1127**                      needs to be or'ed into the status reg. This
     1128**                      also does some other things !!!! caution should
     1129**                      be used if invoking this while in the middle
     1130**                      of a debugging session where the client may have
     1131**                      nested interrupts.
     1132**
     1133****************************************************************************/
     1134FRAME(enable_int,sp,0,ra)
     1135        .set    noreorder
     1136        mfc0    t0,C0_SR
     1137        or      a0,1
     1138        or      t0,a0
     1139        mtc0    t0,C0_SR
     1140        j       ra
     1141        nop
     1142        .set    reorder
     1143ENDFRAME(enable_int)
     1144
     1145
     1146/***************************************************************************
     1147**
     1148**      disable_int(mask) - disable the interrupt - mask is the complement
     1149**                          of the bits to be cleared - i.e. to clear ext int
     1150**                          5 the mask would be - 0xffff7fff
     1151**
     1152****************************************************************************/
     1153FRAME(disable_int,sp,0,ra)
     1154        .set    noreorder
     1155        mfc0    t0,C0_SR
     1156        nop
     1157        and     t0,a0
     1158        mtc0    t0,C0_SR
     1159        j       ra
     1160        nop
     1161ENDFRAME(disable_int)
     1162
     1163
    7351164/*PAGE
    7361165 *
     
    7501179 */
    7511180
     1181#if __mips == 3
     1182
    7521183FRAME(_CPU_Thread_Idle_body,sp,0,ra)
    7531184        wait                    /* enter low power mode */
     
    7561187ENDFRAME(_CPU_Thread_Idle_body)
    7571188
    758 #define VEC_CODE_LENGTH 10*4
     1189#elif __mips == 1
     1190
     1191FRAME(_CPU_Thread_Idle_body,sp,0,ra)
     1192        nop                     /* no wait instruction */
     1193        j _CPU_Thread_Idle_body
     1194        nop
     1195ENDFRAME(_CPU_Thread_Idle_body)
     1196
     1197#else
     1198
     1199   #error "__mips not set to 1 or 3"
     1200   
     1201#endif
    7591202
    7601203/**************************************************************************
     
    7711214***************************************************************************/
    7721215
    773 #define INITEXCFRM ((2*4)+4)            /* ra + 2 arguments */
     1216#define VEC_CODE_LENGTH 10*4
     1217
    7741218FRAME(init_exc_vecs,sp,0,ra)
    775 /* This code yanked from SIM */
    776 #if defined(CPU_R3000)
     1219
     1220#if __mips == 1
     1221
    7771222        .set    noreorder
    7781223        la      t1,exc_utlb_code
     
    7941239        move    t5,ra           # assumes clear_cache doesnt use t5
    7951240        li      a0,UT_VEC
    796         jal     clear_cache
     1241        jal     clear_cache          /* Check out clear cache.... */
    7971242        li      a1,VEC_CODE_LENGTH
    7981243        nop
     
    8041249        nop
    8051250        .set    reorder
    806 #endif
    807 #if defined(CPU_R4000)
     1251
     1252#elif __mips == 3
     1253
    8081254        .set reorder
    8091255        move    t5,ra           # assumes clear_cache doesnt use t5
     
    8751321        move    ra,t5           # restore ra
    8761322        j       ra
    877 #endif
     1323
     1324#else
     1325   #error "__mips not set to 1 or 3"
     1326#endif
     1327
    8781328ENDFRAME(init_exc_vecs)
    879 
    880 
    881 #if defined(CPU_R4000)
    882 FRAME(exc_tlb_code,sp,0,ra)
    883 #ifdef CPU_R3000
    884         la      k0, (R_VEC+((48)*8))
    885 #endif
    886 
    887 #ifdef CPU_R4000
    888         la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    889 #endif
    890         j       k0
    891         nop
    892 
    893 ENDFRAME(exc_tlb_code)
    894 
    895 
    896 FRAME(exc_xtlb_code,sp,0,ra)
    897 #ifdef CPU_R3000
    898         la      k0, (R_VEC+((48)*8))
    899 #endif
    900 
    901 #ifdef CPU_R4000
    902         la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    903 #endif
    904         j       k0
    905         nop
    906 
    907 ENDFRAME(exc_xtlb_code)
    908 
    909 
    910 FRAME(exc_cache_code,sp,0,ra)
    911 #ifdef CPU_R3000
    912         la      k0, (R_VEC+((48)*8))
    913 #endif
    914 
    915 #ifdef CPU_R4000
    916         la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    917 #endif
    918         j       k0
    919         nop
    920 
    921 ENDFRAME(exc_cache_code)
    922 
    9231329
    9241330FRAME(exc_norm_code,sp,0,ra)
     
    9261332        j       k0
    9271333        nop
    928         subu    sp, EXCP_STACK_SIZE             /* set up local stack frame */
    9291334ENDFRAME(exc_norm_code)
    930 #endif
    931 
    932 /**************************************************************************
    933 **
    934 ** enable_int(mask) - enables interrupts - mask is positioned so it only
    935 **                      needs to be or'ed into the status reg. This
    936 **                      also does some other things !!!! caution should
    937 **                      be used if invoking this while in the middle
    938 **                      of a debugging session where the client may have
    939 **                      nested interrupts.
    940 **
    941 ****************************************************************************/
    942 FRAME(enable_int,sp,0,ra)
    943         .set    noreorder
    944         mfc0    t0,C0_SR
    945         or      a0,1
    946         or      t0,a0
    947         mtc0    t0,C0_SR
    948         j       ra
    949         nop
    950         .set    reorder
    951 ENDFRAME(enable_int)
    952 
    953 
    954 /***************************************************************************
    955 **
    956 **      disable_int(mask) - disable the interrupt - mask is the complement
    957 **                          of the bits to be cleared - i.e. to clear ext int
    958 **                          5 the mask would be - 0xffff7fff
    959 **
    960 ****************************************************************************/
    961 FRAME(disable_int,sp,0,ra)
    962         .set    noreorder
    963         mfc0    t0,C0_SR
    964         nop
    965         and     t0,a0
    966         mtc0    t0,C0_SR
    967         j       ra
    968         nop
    969 ENDFRAME(disable_int)
    970 
    971 
     1335
     1336/*
     1337** Again, reliance on SIM. Not good.
     1338*/
     1339#if __mips == 3
     1340
     1341FRAME(exc_tlb_code,sp,0,ra)
     1342        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
     1343        j       k0
     1344        nop
     1345ENDFRAME(exc_tlb_code)
     1346
     1347FRAME(exc_xtlb_code,sp,0,ra)
     1348        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
     1349        j       k0
     1350        nop
     1351
     1352ENDFRAME(exc_xtlb_code)
     1353
     1354FRAME(exc_cache_code,sp,0,ra)
     1355        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
     1356        j       k0
     1357        nop
     1358ENDFRAME(exc_cache_code)
     1359
     1360#elif __mips == 1
     1361/* ------------------------------------------------------ */
     1362FRAME(exc_tlb_code,sp,0,ra)
     1363        la      k0, (R_VEC+((48)*8))  /* Need something else here besides IDT/SIM call */
     1364        j       k0
     1365        nop
     1366ENDFRAME(exc_tlb_code)
     1367
     1368FRAME(exc_cache_code,sp,0,ra)
     1369        la      k0, (R_VEC+((48)*8))
     1370        j       k0
     1371        nop
     1372ENDFRAME(exc_cache_code)
     1373
     1374#else
     1375
     1376   #error "__mips is not set to 1 or 3"
     1377
     1378#endif
     1379
  • c/src/exec/score/cpu/mips/cpu_asm.h

    r6bb5260 rfda47cd  
    1717 *      of this software for any purpose.
    1818 *
    19  *  Derived from source copyrighted as follows:
     19 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h:
    2020 *
    2121 *  COPYRIGHT (c) 1989-1999.
  • c/src/exec/score/cpu/mips/idtcpu.h

    r6bb5260 rfda47cd  
    4646#define K2BASE  0xc0000000
    4747#define K2SIZE  0x20000000
    48 #if defined(CPU_R4000)
     48#if  __mips == 3
    4949#define KSBASE  0xe0000000
    5050#define KSSIZE  0x20000000
     
    5757** Exception Vectors
    5858*/
    59 #if defined(CPU_R3000)
     59#if  __mips == 1
    6060#define UT_VEC  K0BASE                  /* utlbmiss vector */
    6161#define E_VEC   (K0BASE+0x80)           /* exception vevtor */
    6262#endif
    63 #if defined(CPU_R4000)
     63#if  __mips == 3
    6464#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
    6565#define X_VEC   (K0BASE+0x080)          /* xtlbmiss vector */
     
    9090#define MAXCACHE        0x40000         /* 256*1024   256k */   
    9191
    92 #if defined(CPU_R4000)
     92#if  __mips == 3
    9393/* R4000 configuration register definitions */
    9494#define CFG_CM          0x80000000      /* Master-Checker mode */
     
    185185** TLB resource defines
    186186*/
    187 #if defined(CPU_R3000)
     187#if  __mips == 1
    188188#define N_TLB_ENTRIES   64
    189189#define TLB_PGSIZE      0x1000
     
    215215#define TLBCTXT_VPNSHIFT        2
    216216#endif
    217 #if defined(CPU_R4000)
     217#if  __mips == 3
    218218#define N_TLB_ENTRIES   48
    219219
     
    250250#endif
    251251
    252 #if defined(CPU_R3000)
     252#if  __mips == 1
    253253#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    254254#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     
    301301#endif
    302302
    303 #if defined(CPU_R4000)
     303#if  __mips == 3
    304304#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    305305#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     
    376376#define C0_INX          $0              /* tlb index */
    377377#define C0_RAND         $1              /* tlb random */
    378 #if defined(CPU_R3000)
     378#if  __mips == 1
    379379#define C0_TLBLO        $2              /* tlb entry low */
    380380#endif
    381 #if defined(CPU_R4000)
     381#if  __mips == 3
    382382#define C0_TLBLO0       $2              /* tlb entry low 0 */
    383383#define C0_TLBLO1       $3              /* tlb entry low 1 */
     
    386386#define C0_CTXT         $4              /* tlb context */
    387387
    388 #if defined(CPU_R4000)
     388#if  __mips == 3
    389389#define C0_PAGEMASK     $5              /* tlb page mask */
    390390#define C0_WIRED        $6              /* number of wired tlb entries */
     
    393393#define C0_BADVADDR     $8              /* bad virtual address */
    394394
    395 #if defined(CPU_R4000)
     395#if  __mips == 3
    396396#define C0_COUNT        $9              /* cycle count */
    397397#endif
     
    399399#define C0_TLBHI        $10             /* tlb entry hi */
    400400
    401 #if defined(CPU_R4000)
     401#if  __mips == 3
    402402#define C0_COMPARE      $11             /* cyccle count comparator  */
    403403#endif
     
    408408#define C0_PRID         $15             /* revision identifier */
    409409
    410 #if defined(CPU_R3000)
     410#if  __mips == 1
    411411#define C0_CONFIG   $3     /* configuration register R3081*/
    412412#endif
    413413
    414 #if defined(CPU_R4000)
     414#if  __mips == 3
    415415#define C0_CONFIG       $16             /* configuration register */
    416416#define C0_LLADDR       $17             /* linked load address */
  • c/src/exec/score/cpu/mips/iregdef.h

    r6bb5260 rfda47cd  
    222222#define R_CAUSE         68
    223223#define R_TLBHI         69
    224 #if defined(CPU_R3000)
     224#if __mips == 1
    225225#define R_TLBLO         70
    226226#endif
    227 #if defined(CPU_R4000)
     227#if  __mips == 3
    228228#define R_TLBLO0        70
    229229#endif
     
    237237#define R_FCSR          78
    238238#define R_FEIR          79
    239 #if defined(CPU_R3000)
     239#if __mips == 1
    240240#define NREGS           80
    241241#endif
    242 #if defined(CPU_R4000)
     242#if  __mips == 3
    243243#define R_TLBLO1        80
    244244#define R_PAGEMASK      81
     
    297297
    298298/* Ketan added the following */
    299 #ifdef CPU_R3000
     299#ifdef __mips == 1
    300300#define sreg    sw
    301301#define lreg    lw
     
    303303#define rmtc0   mtc0
    304304#define R_SZ    4
    305 #endif CPU_R3000
    306 
    307 #ifdef CPU_R4000
     305#endif /* __mips == 1 */
     306
     307/* #ifdef  __mips == 3 */
    308308#if __mips < 3
    309309#define sreg    sw
     
    319319#define R_SZ    8
    320320#endif
    321 #endif CPU_R4000
     321/* #endif __mips == 3 */
    322322/* Ketan till here */
    323323
  • c/src/exec/score/cpu/mips/rtems/score/cpu.h

    r6bb5260 rfda47cd  
    1919 *      of this software for any purpose.
    2020 *
    21  *  Derived from source copyrighted as follows:
     21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
    2222 *
    2323 *  COPYRIGHT (c) 1989-1999.
     
    9494 *  Does RTEMS manage a dedicated interrupt stack in software?
    9595 *
    96  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
     96 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
    9797 *  If FALSE, nothing is done.
    9898 *
     
    163163 *  the answer is TRUE.
    164164 *
    165  *  The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
     165 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
    166166 *  It indicates whether or not this CPU model has FP support.  For
    167167 *  example, it would be possible to have an i386_nofp CPU model
     
    170170 */
    171171
    172 #if ( MIPS64ORION_HAS_FPU == 1 )
     172#if ( MIPS_HAS_FPU == 1 )
    173173#define CPU_HARDWARE_FP     TRUE
    174174#else
    175175#define CPU_HARDWARE_FP     FALSE
    176176#endif
    177 #define CPU_SOFTWARE_FP     FALSE
    178177
    179178/*
     
    445444
    446445/*
    447  *  Macros to access MIPS64ORION specific additions to the CPU Table
     446 *  Macros to access MIPS specific additions to the CPU Table
    448447 */
    449448
  • c/src/exec/score/cpu/mips/rtems/score/mips.h

    r6bb5260 rfda47cd  
    1616 *      of this software for any purpose.
    1717 *
    18  *  Derived from source copyrighted as follows:
     18 *  Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h:
    1919 *
    2020 *  COPYRIGHT (c) 1989-1999.
     
    2929/* @(#)mips64orion.h       08/29/96     1.3 */
    3030
    31 #ifndef _INCLUDE_MIPS64ORION_h
    32 #define _INCLUDE_MIPS64ORION_h
     31#ifndef _INCLUDE_MIPS_h
     32#define _INCLUDE_MIPS_h
    3333
    3434#ifdef __cplusplus
     
    4545 */
    4646 
    47 #if defined(rtems_multilib)
    48 /*
    49  *  Figure out all CPU Model Feature Flags based upon compiler
    50  *  predefines.
    51  */
     47#if defined(__mips_soft_float)
     48#define MIPS_HAS_FPU 0
     49#else
     50#define MIPS_HAS_FPU 1
     51#endif
    5252
    53 #define CPU_MODEL_NAME  "rtems_multilib"
    54 #define MIPS64ORION_HAS_FPU     1
    55 
    56 #elif defined(R4650)
    57  
    58 #define CPU_MODEL_NAME  "R4650"
    59 #define MIPS64ORION_HAS_FPU     1
    60  
    61 #elif defined(R4600)
    62  
    63 #define CPU_MODEL_NAME  "R4600"
    64 #define MIPS64ORION_HAS_FPU     1
    65 
     53#if (__mips == 1)
     54#define CPU_MODEL_NAME  "ISA Level 1 or 2"
     55#elif (__mips == 3)
     56#if defined(__mips64)
     57#define CPU_MODEL_NAME  "ISA Level 4"
    6658#else
    67  
    68 #error "Unsupported CPU Model"
    69  
     59#define CPU_MODEL_NAME  "ISA Level 3"
     60#endif
     61#else
     62#error "Unknown MIPS ISA level"
    7063#endif
    7164
     
    7467 */
    7568
    76 #define CPU_NAME "MIPS R46xxx"
     69#define CPU_NAME "MIPS"
    7770
    7871#ifdef __cplusplus
     
    8073#endif
    8174
    82 #endif /* ! _INCLUDE_MIPS64ORION_h */
     75#endif /* ! _INCLUDE_MIPS_h */
    8376/* end of include file */
  • c/src/exec/score/cpu/mips/rtems/score/mips64orion.h

    r6bb5260 rfda47cd  
    1616 *      of this software for any purpose.
    1717 *
    18  *  Derived from source copyrighted as follows:
     18 *  Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h:
    1919 *
    2020 *  COPYRIGHT (c) 1989-1999.
     
    2929/* @(#)mips64orion.h       08/29/96     1.3 */
    3030
    31 #ifndef _INCLUDE_MIPS64ORION_h
    32 #define _INCLUDE_MIPS64ORION_h
     31#ifndef _INCLUDE_MIPS_h
     32#define _INCLUDE_MIPS_h
    3333
    3434#ifdef __cplusplus
     
    4545 */
    4646 
    47 #if defined(rtems_multilib)
    48 /*
    49  *  Figure out all CPU Model Feature Flags based upon compiler
    50  *  predefines.
    51  */
     47#if defined(__mips_soft_float)
     48#define MIPS_HAS_FPU 0
     49#else
     50#define MIPS_HAS_FPU 1
     51#endif
    5252
    53 #define CPU_MODEL_NAME  "rtems_multilib"
    54 #define MIPS64ORION_HAS_FPU     1
    55 
    56 #elif defined(R4650)
    57  
    58 #define CPU_MODEL_NAME  "R4650"
    59 #define MIPS64ORION_HAS_FPU     1
    60  
    61 #elif defined(R4600)
    62  
    63 #define CPU_MODEL_NAME  "R4600"
    64 #define MIPS64ORION_HAS_FPU     1
    65 
     53#if (__mips == 1)
     54#define CPU_MODEL_NAME  "ISA Level 1 or 2"
     55#elif (__mips == 3)
     56#if defined(__mips64)
     57#define CPU_MODEL_NAME  "ISA Level 4"
    6658#else
    67  
    68 #error "Unsupported CPU Model"
    69  
     59#define CPU_MODEL_NAME  "ISA Level 3"
     60#endif
     61#else
     62#error "Unknown MIPS ISA level"
    7063#endif
    7164
     
    7467 */
    7568
    76 #define CPU_NAME "MIPS R46xxx"
     69#define CPU_NAME "MIPS"
    7770
    7871#ifdef __cplusplus
     
    8073#endif
    8174
    82 #endif /* ! _INCLUDE_MIPS64ORION_h */
     75#endif /* ! _INCLUDE_MIPS_h */
    8376/* end of include file */
  • cpukit/score/cpu/mips/ChangeLog

    r6bb5260 rfda47cd  
     12000-10-24      Alan Cudmore <alanc@linuxstart.com> and
     2        Joel Sherrill <joel@OARcorp.com>
     3
     4        * This is a major reworking of the mips64orion port to use
     5        gcc predefines as much as possible and a big push to multilib
     6        the mips port.  The mips64orion port was copied/renamed to mips
     7        to be more like other GNU tools.  Alan did most of the technical
     8        work of determining how to map old macro names used by the mips64orion
     9        port to standard compiler macro definitions.  Joel did the merge
     10        with CVS magic to keep individual file history and did the BSP
     11        modifications. Details follow:
     12        * Makefile.am: idtmon.h in mips64orion port not present.
     13        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
     14        * cpu.c: Comments added.
     15        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
     16        First attempt at exception/interrupt processing for ISA level 1
     17        and minus any use of IDT/MON added.
     18        * idtcpu.h: Conditionals changed to use gcc predefines.
     19        * iregdef.h: Ditto.
     20        * cpu_asm.h: No real change.  Merger required commit.
     21        * rtems/Makefile.am: Ditto.
     22        * rtems/score/Makefile.am: Ditto.
     23        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
     24        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
     25        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
     26
    1272000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    228
  • cpukit/score/cpu/mips/Makefile.am

    r6bb5260 rfda47cd  
    1111C_O_FILES = $(C_FILES:%.c=$(ARCH)/%.o)
    1212
    13 H_FILES = asm.h cpu_asm.h idtcpu.h idtmon.h iregdef.h
     13H_FILES = asm.h cpu_asm.h idtcpu.h iregdef.h
    1414
    1515S_FILES = cpu_asm.S
     
    4545.PRECIOUS: $(REL)
    4646
    47 EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h idtmon.h iregdef.h \
     47EXTRA_DIST = asm.h cpu.c cpu_asm.S cpu_asm.h idtcpu.h iregdef.h \
    4848    rtems.c
    4949
  • cpukit/score/cpu/mips/asm.h

    r6bb5260 rfda47cd  
    2525/* @(#)asm.h       03/15/96     1.1 */
    2626
    27 #ifndef __MIPS64ORION_ASM_h
    28 #define __MIPS64ORION_ASM_h
     27#ifndef __NO_CPU_ASM_h
     28#define __NO_CPU_ASM_h
    2929
    3030/*
     
    9797#define EXTERN(sym) .globl SYM (sym)
    9898
     99/*
     100 *  Debugger macros for assembly language routines. Allows the
     101 *  programmer to set up the necessary stack frame info
     102 *  required by debuggers to do stack traces.
     103 */
     104
     105#ifndef XDS
     106#define FRAME(name,frm_reg,offset,ret_reg)      \
     107        .globl  name;                           \
     108        .ent    name;                           \
     109name:;                                          \
     110        .frame  frm_reg,offset,ret_reg
     111#define ENDFRAME(name)                          \
     112        .end name
     113#else
     114#define FRAME(name,frm_reg,offset,ret_reg)      \
     115        .globl  _##name;\
     116_##name:
     117#define ENDFRAME(name)
     118#endif  XDS
     119
    99120#endif
    100121/* end of include file */
    101122
    102 
  • cpukit/score/cpu/mips/cpu.c

    r6bb5260 rfda47cd  
    22 *  Mips CPU Dependent Source
    33 *
    4  *  Author:     Craig Lebakken <craigl@transition.com>
    5  *
    6  *  COPYRIGHT (c) 1996 by Transition Networks Inc.
    7  *
    8  *  To anyone who acknowledges that this file is provided "AS IS"
    9  *  without any express or implied warranty:
    10  *      permission to use, copy, modify, and distribute this file
    11  *      for any purpose is hereby granted without fee, provided that
    12  *      the above copyright notice and this notice appears in all
    13  *      copies, and that the name of Transition Networks not be used in
    14  *      advertising or publicity pertaining to distribution of the
    15  *      software without specific, written prior permission.
    16  *      Transition Networks makes no representations about the suitability
    17  *      of this software for any purpose.
    18  *
    19  *  Derived from source copyrighted as follows:
     4 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
     5 *           Joel Sherrill <joel@OARcorp.com>.
     6 *
     7 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
     8 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
     9 *
     10 *         To anyone who acknowledges that this file is provided "AS IS"
     11 *         without any express or implied warranty:
     12 *             permission to use, copy, modify, and distribute this file
     13 *             for any purpose is hereby granted without fee, provided that
     14 *             the above copyright notice and this notice appears in all
     15 *             copies, and that the name of Transition Networks not be used in
     16 *             advertising or publicity pertaining to distribution of the
     17 *             software without specific, written prior permission.
     18 *             Transition Networks makes no representations about the
     19 *             suitability of this software for any purpose.
     20 *
     21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.c:
    2022 *
    2123 *  COPYRIGHT (c) 1989-1999.
     
    125127   *  table used by the CPU to dispatch interrupt handlers.
    126128   */
    127 
     129/* Q: This will become necessary for Non IDT/Sim use...*/
    128130#if 0 /* not necessary */
    129131/* use IDT/Sim to set interrupt vector.  Needed to co-exist with debugger. */
  • cpukit/score/cpu/mips/cpu_asm.S

    r6bb5260 rfda47cd  
    2020 *      of this software for any purpose.
    2121 *
    22  *  Derived from source copyrighted as follows:
     22 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
    2323 *
    2424 *  COPYRIGHT (c) 1989-1999.
     
    4646        .end name
    4747
    48 
    4948#define EXCP_STACK_SIZE (NREGS*R_SZ)
    50 
    51 #if __ghs__
    52 #define sd sw
    53 #define ld lw
    54 #define dmtc0 mtc0
    55 #define dsll sll
    56 #define dmfc0 mfc0
    57 #endif
     49#define ISR_VEC_SIZE 4
    5850
    5951#if 1  /* 32 bit unsigned32 types */
     
    142134}
    143135#endif
     136
     137#if __mips == 3
    144138/* return the current exception level for the 4650 */
    145139FRAME(_CPU_ISR_Get_level,sp,0,ra)
     
    164158        bnez a0,_CPU_ISR_Set_2
    165159        nop
    166         nop
    167         mfc0 t0,C0_SR
     160        nop
     161        mfc0 t0, C0_SR
    168162        nop
    169163        li t1,~SR_EXL
     
    183177        mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
    184178        nop
    185         ori t0,SR_EXL|SR_IE             /* enable exception level  */
     179        ori  t0, SR_EXL|SR_IE           /* enable exception level */   
    186180        nop
    187181        mtc0 t0,C0_SR         
     
    191185        nop
    192186ENDFRAME(_CPU_ISR_Set_level)
     187
     188#elif __mips == 1
     189
     190/* MIPS ISA 1 ( R3000 ) */
     191/* These routines might not be needed for the R3000 */
     192/* Q:Who calls _CPU_ISR_Get/Set_level? */
     193FRAME(_CPU_ISR_Get_level,sp,0,ra)
     194        mfc0 v0,C0_SR
     195        nop
     196        andi v0, SR_IEC
     197        j ra
     198ENDFRAME(_CPU_ISR_Get_level)
     199
     200FRAME(_CPU_ISR_Set_level,sp,0,ra)
     201        nop
     202        mfc0 t0,C0_SR
     203        andi a0, SR_IEC
     204        or   t0, a0
     205        mtc0 t0,C0_SR
     206        nop
     207        j ra
     208ENDFRAME(_CPU_ISR_Set_level)
     209
     210#else
     211   #error "__mips is set to 1 or 3"
     212#endif
    193213
    194214/*
     
    324344 * }
    325345 */
     346#if __mips == 3
     347/* MIPS ISA Level 3 ( R4xxx ) */
    326348
    327349FRAME(_CPU_Context_switch,sp,0,ra)
     
    338360        sd sp,SP_OFFSET*8(a0)
    339361        sd fp,FP_OFFSET*8(a0)
    340         sd s0,S0_OFFSET*8(a0)
    341362        sd s1,S1_OFFSET*8(a0)
    342363        sd s2,S2_OFFSET*8(a0)
     
    376397ENDFRAME(_CPU_Context_switch)
    377398
     399#elif __mips == 1
     400/* MIPS ISA Level 1 ( R3000 ) */
     401
     402FRAME(_CPU_Context_switch,sp,0,ra)
     403
     404        mfc0 t0,C0_SR
     405        li t1,~SR_IEC
     406        sw t0,C0_SR_OFFSET*4(a0)        /* save status register */
     407        and t0,t1
     408        mtc0 t0,C0_SR                   /* first disable ie bit (recommended) */
     409
     410        sw ra,RA_OFFSET*4(a0)           /* save current context */
     411        sw sp,SP_OFFSET*4(a0)
     412        sw fp,FP_OFFSET*4(a0)
     413        sw s0,S0_OFFSET*4(a0)
     414        sw s1,S1_OFFSET*4(a0)
     415        sw s2,S2_OFFSET*4(a0)
     416        sw s3,S3_OFFSET*4(a0)
     417        sw s4,S4_OFFSET*4(a0)
     418        sw s5,S5_OFFSET*4(a0)
     419        sw s6,S6_OFFSET*4(a0)
     420        sw s7,S7_OFFSET*4(a0)
     421
     422        mfc0 t0,C0_EPC
     423        sw t0,C0_EPC_OFFSET*4(a0)
     424
     425_CPU_Context_switch_restore:
     426        lw s0,S0_OFFSET*4(a1)           /* restore context */
     427        lw s1,S1_OFFSET*4(a1)
     428        lw s2,S2_OFFSET*4(a1)
     429        lw s3,S3_OFFSET*4(a1)
     430        lw s4,S4_OFFSET*4(a1)
     431        lw s5,S5_OFFSET*4(a1)
     432        lw s6,S6_OFFSET*4(a1)
     433        lw s7,S7_OFFSET*4(a1)
     434        lw fp,FP_OFFSET*4(a1)
     435        lw sp,SP_OFFSET*4(a1)
     436        lw ra,RA_OFFSET*4(a1)
     437        lw t0,C0_EPC_OFFSET*4(a1)
     438        mtc0 t0,C0_EPC
     439        lw t1, C0_SR_OFFSET*4(a1)
     440        mtc0 t1,C0_SR
     441
     442        /* Q:Changes needed to SR_IEC bit in SR/_CPU_Context_switch_restore? */
     443
     444_CPU_Context_1:
     445        j ra
     446        nop
     447ENDFRAME(_CPU_Context_switch)
     448
     449#else
     450
     451   #error "__mips is not set to 1 or 3"
     452
     453#endif
     454
    378455/*
    379456 *  _CPU_Context_restore
     
    393470#endif
    394471
     472#if __mips == 3
     473
    395474FRAME(_CPU_Context_restore,sp,0,ra)
    396475        dadd a1,a0,zero
     
    398477        nop
    399478ENDFRAME(_CPU_Context_restore)
     479
     480#elif __mips == 1
     481
     482FRAME(_CPU_Context_restore,sp,0,ra)
     483        add  a1,a0,zero
     484        j _CPU_Ccontext_switch_restore
     485        nop
     486ENDFRAME(_CPU_Context_restore)
     487
     488#else
     489
     490      #error "__mips is not set to 1 or 3"
     491
     492#endif
    400493
    401494EXTERN(_ISR_Nest_level, SZ_INT)
     
    439532   */
    440533#endif
     534
     535#if __mips == 3
     536/* ----------------------------------------------------------------------------- */
    441537FRAME(_ISR_Handler,sp,0,ra)
    442538.set noreorder
     
    488584        mfc0 k0,C0_CAUSE
    489585        and k1,k0,CAUSE_EXCMASK
    490         bnez k1,_ISR_Handler_prom_exit /* not an external interrupt, pass exception to Monitor */
    491         mfc0 k1,C0_SR
     586        bnez k1,_ISR_Handler_prom_exit /* not an external interrup
     587t, pass exception to Monitor */
     588        mfc0 k1,C0_SR
    492589        and k0,k1
    493590        and k0,CAUSE_IPMASK
     
    662759
    663760_ISR_Handler_prom_exit:
    664 #ifdef CPU_R3000
     761#if __mips == 1
    665762        la      k0, (R_VEC+((48)*8))
    666763#endif
    667764
    668 #ifdef CPU_R4000
     765#if __mips == 3
    669766        la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    670767#endif
     
    676773ENDFRAME(_ISR_Handler)
    677774
     775/* ---------------------------------------------------------------------- */
     776#elif __mips == 1
     777/* MIPS ISA Level 1 */
     778
     779FRAME(_ISR_Handler,sp,0,ra)
     780.set noreorder
     781
     782        /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */
     783
     784        addiu sp,sp,-EXCP_STACK_SIZE       /* wastes alot of stack space for context?? */
     785
     786        sw    ra, R_RA*R_SZ(sp)  /* store ra on the stack */
     787        sw    v0, R_V0*R_SZ(sp)
     788        sw    v1, R_V1*R_SZ(sp)
     789        sw    a0, R_A0*R_SZ(sp)
     790        sw    a1, R_A1*R_SZ(sp)
     791        sw    a2, R_A2*R_SZ(sp)
     792        sw    a3, R_A3*R_SZ(sp)
     793        sw    t0, R_T0*R_SZ(sp)
     794        sw    t1, R_T1*R_SZ(sp)
     795        sw    t2, R_T2*R_SZ(sp)
     796        sw    t3, R_T3*R_SZ(sp)
     797        sw    t4, R_T4*R_SZ(sp)
     798        sw    t5, R_T5*R_SZ(sp)
     799        sw    t6, R_T6*R_SZ(sp)
     800        sw    t7, R_T7*R_SZ(sp)
     801        mflo    k0
     802        sw    t8, R_T8*R_SZ(sp)
     803        sw    k0, R_MDLO*R_SZ(sp)
     804        sw    t9, R_T9*R_SZ(sp)
     805        mfhi    k0
     806        sw    gp, R_GP*R_SZ(sp)
     807        sw    fp, R_FP*R_SZ(sp)
     808        sw    k0, R_MDHI*R_SZ(sp)
     809        .set noat
     810        sw    AT, R_AT*R_SZ(sp)
     811        .set at
     812
     813        /* Q: Why hardcode -40 for stack add??? */
     814        /* This needs to be figured out.........*/
     815        addiu sp,sp,-40
     816        sw ra,32(sp)    /* store ra on the stack */
     817
     818/* determine if an interrupt generated this exception */
     819
     820        mfc0 k0,C0_CAUSE
     821        and k1,k0,CAUSE_EXCMASK
     822        beq k1, 0, _ISR_Handler_1
     823        nop
     824
     825_ISR_Handler_Exception:
     826        nop
     827        b  _ISR_Handler_Exception       /* Jump to the exception code */
     828        nop
     829
     830_ISR_Handler_1:
     831
     832        mfc0 k1,C0_SR
     833        and k0,k1
     834        and k0,CAUSE_IPMASK
     835        beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */
     836                                      /* but if it's not an exception or an interrupt,
     837                                      /* Then where did it come from??? */
     838        nop
     839
     840  /*
     841   *  save some or all context on stack
     842   *  may need to save some special interrupt information for exit
     843   *
     844   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
     845   *    if ( _ISR_Nest_level == 0 )
     846   *      switch to software interrupt stack
     847   *  #endif
     848   */
     849
     850  /*
     851   *  _ISR_Nest_level++;
     852   */
     853        lw   t0,_ISR_Nest_level
     854        addi t0,t0,1
     855        sw   t0,_ISR_Nest_level
     856  /*
     857   *  _Thread_Dispatch_disable_level++;
     858   */
     859        lw   t1,_Thread_Dispatch_disable_level
     860        addi t1,t1,1
     861        sw   t1,_Thread_Dispatch_disable_level
     862
     863  /*
     864   *  while ( interrupts_pending(cause_reg) ) {
     865   *     vector = BITFIELD_TO_INDEX(cause_reg);
     866   *     (*_ISR_Vector_table[ vector ])( vector );
     867   *  }
     868   */
     869        /* k0 has the SR interrupt bits */
     870        la t3, _ISR_vector_table
     871
     872        /* The bits you look at can be prioritized here just by */
     873        /*  changing what bit is looked at. I.E. SR_IBITx */
     874        /* This code might become a loop, servicing all ints before returning.. */
     875        /*   Right now, it will go thru the whole list once */
     876
     877_ISR_check_bit_0:
     878        and k1, k0, SR_IBIT1
     879        beq k1, zero, _ISR_check_bit_1
     880        nop
     881        li  t1, ISR_VEC_SIZE*0
     882        add t3, t1
     883        jal t3 
     884        nop
     885_ISR_check_bit_1:
     886        and k1, k0, SR_IBIT2
     887        beq k1, zero, _ISR_check_bit_2
     888        nop
     889        li  t1, ISR_VEC_SIZE*1
     890        add t3, t1
     891        jal t3
     892        nop
     893_ISR_check_bit_2:
     894        and k1, k0, SR_IBIT3
     895        beq k1, zero, _ISR_check_bit_3
     896        nop
     897        li  t1, ISR_VEC_SIZE*2
     898        add t3, t1
     899        jal t3
     900        nop
     901_ISR_check_bit_3:
     902        and k1, k0, SR_IBIT4
     903        beq k1, zero, _ISR_check_bit_4
     904        nop
     905        li  t1, ISR_VEC_SIZE*3
     906        add t3, t1
     907        jal t3
     908        nop
     909_ISR_check_bit_4:
     910        and k1, k0, SR_IBIT5
     911        beq k1, zero, _ISR_check_bit_5
     912        nop
     913        li  t1, ISR_VEC_SIZE*4
     914        add t3, t1
     915        jal t3
     916        nop
     917_ISR_check_bit_5:
     918        and k1, k0, SR_IBIT6
     919        beq k1, zero, _ISR_check_bit_6
     920        nop
     921        li  t1, ISR_VEC_SIZE*5
     922        add t3, t1
     923        jal t3
     924        nop
     925_ISR_check_bit_6:
     926        and k1, k0, SR_IBIT7
     927        beq k1, zero, _ISR_check_bit_7
     928        nop
     929        li  t1, ISR_VEC_SIZE*6
     930        add t3, t1
     931        jal t3
     932        nop
     933_ISR_check_bit_7:
     934        and k1, k0, SR_IBIT8
     935        beq k1, zero, _ISR_exit_int_check
     936        nop
     937        li  t1, ISR_VEC_SIZE*7
     938        add t3, t1
     939        jal t3
     940        nop
     941
     942_ISR_exit_int_check:
     943
     944  /*
     945   *  --_ISR_Nest_level;
     946   */
     947        lw   t2,_ISR_Nest_level
     948        addi t2,t2,-1
     949        sw   t2,_ISR_Nest_level
     950  /*
     951   *  --_Thread_Dispatch_disable_level;
     952   */
     953        lw   t1,_Thread_Dispatch_disable_level
     954        addi t1,t1,-1
     955        sw   t1,_Thread_Dispatch_disable_level
     956  /*
     957   *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
     958   *    goto the label "exit interrupt (simple case)"
     959   */
     960        or  t0,t2,t1
     961        bne t0,zero,_ISR_Handler_exit
     962        nop
     963  /*
     964   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
     965   *    restore stack
     966   *  #endif
     967   * 
     968   *  if ( !_Context_Switch_necessary && !_ISR_Signals_to_thread_executing )
     969   *    goto the label "exit interrupt (simple case)"
     970   */
     971        lw  t0,_Context_Switch_necessary
     972        lw  t1,_ISR_Signals_to_thread_executing
     973        or  t0,t0,t1
     974        beq t0,zero,_ISR_Handler_exit
     975        nop
     976  /*
     977   *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
     978   */
     979        jal _Thread_Dispatch
     980        nop
     981  /*
     982   *  prepare to get out of interrupt
     983   *  return from interrupt  (maybe to _ISR_Dispatch)
     984   *
     985   *  LABEL "exit interrupt (simple case):
     986   *  prepare to get out of interrupt
     987   *  return from interrupt
     988   */
     989
     990_ISR_Handler_exit:
     991        ld ra,32(sp)
     992        addiu sp,sp,40    /* Q: Again with the 40...Is this needed? */
     993
     994/* restore interrupt context from stack */
     995     
     996        lw    k0, R_MDLO*R_SZ(sp)           
     997        mtlo  k0
     998        lw    k0, R_MDHI*R_SZ(sp)           
     999        lw    a2, R_A2*R_SZ(sp)
     1000        mthi  k0
     1001        lw    a3, R_A3*R_SZ(sp)
     1002        lw    t0, R_T0*R_SZ(sp)
     1003        lw    t1, R_T1*R_SZ(sp)
     1004        lw    t2, R_T2*R_SZ(sp)
     1005        lw    t3, R_T3*R_SZ(sp)
     1006        lw    t4, R_T4*R_SZ(sp)
     1007        lw    t5, R_T5*R_SZ(sp)
     1008        lw    t6, R_T6*R_SZ(sp)
     1009        lw    t7, R_T7*R_SZ(sp)
     1010        lw    t8, R_T8*R_SZ(sp)
     1011        lw    t9, R_T9*R_SZ(sp)
     1012        lw    gp, R_GP*R_SZ(sp)
     1013        lw    fp, R_FP*R_SZ(sp)
     1014        lw    ra, R_RA*R_SZ(sp)
     1015        lw    a0, R_A0*R_SZ(sp)
     1016        lw    a1, R_A1*R_SZ(sp)
     1017        lw    v1, R_V1*R_SZ(sp)
     1018        lw    v0, R_V0*R_SZ(sp)
     1019        .set noat
     1020        lw    AT, R_AT*R_SZ(sp)
     1021        .set at
     1022
     1023        addiu sp,sp,EXCP_STACK_SIZE
     1024       
     1025        rfe  /* Might not need to do RFE here... */
     1026        j ra
     1027        nop
     1028
     1029       .set    reorder
     1030ENDFRAME(_ISR_Handler)
     1031
     1032#else
     1033
     1034   #error "__mips is not set to 1 or 3 "
     1035
     1036#endif
    6781037
    6791038FRAME(mips_enable_interrupts,sp,0,ra)
     
    6971056ENDFRAME(mips_disable_interrupts)
    6981057
     1058#if __mips == 3
     1059
    6991060FRAME(mips_enable_global_interrupts,sp,0,ra)
    7001061        mfc0 t0,C0_SR           /* get status reg */
     
    7161077ENDFRAME(mips_disable_global_interrupts)
    7171078
     1079#elif __mips == 1
     1080
     1081FRAME(mips_enable_global_interrupts,sp,0,ra)
     1082        mfc0 t0,C0_SR           /* get status reg */
     1083        nop
     1084        ori t0,SR_IEC
     1085        mtc0 t0,C0_SR           /* save updated status reg */
     1086        j ra
     1087        nop
     1088ENDFRAME(mips_enable_global_interrupts)
     1089
     1090FRAME(mips_disable_global_interrupts,sp,0,ra)
     1091        li t1,SR_IEC
     1092        mfc0 t0,C0_SR           /* get status reg */
     1093        not t1
     1094        and t0,t1
     1095        mtc0 t0,C0_SR           /* save updated status reg */
     1096        j ra
     1097        nop
     1098ENDFRAME(mips_disable_global_interrupts)
     1099
     1100#else
     1101
     1102   #error "__mips is not set to 1 or 3"
     1103
     1104#endif
     1105
    7181106/* return the value of the status register in v0.  Used for debugging */
    7191107FRAME(mips_get_sr,sp,0,ra)
     
    7331121ENDFRAME(mips_break)
    7341122
     1123
     1124/**************************************************************************
     1125**
     1126** enable_int(mask) - enables interrupts - mask is positioned so it only
     1127**                      needs to be or'ed into the status reg. This
     1128**                      also does some other things !!!! caution should
     1129**                      be used if invoking this while in the middle
     1130**                      of a debugging session where the client may have
     1131**                      nested interrupts.
     1132**
     1133****************************************************************************/
     1134FRAME(enable_int,sp,0,ra)
     1135        .set    noreorder
     1136        mfc0    t0,C0_SR
     1137        or      a0,1
     1138        or      t0,a0
     1139        mtc0    t0,C0_SR
     1140        j       ra
     1141        nop
     1142        .set    reorder
     1143ENDFRAME(enable_int)
     1144
     1145
     1146/***************************************************************************
     1147**
     1148**      disable_int(mask) - disable the interrupt - mask is the complement
     1149**                          of the bits to be cleared - i.e. to clear ext int
     1150**                          5 the mask would be - 0xffff7fff
     1151**
     1152****************************************************************************/
     1153FRAME(disable_int,sp,0,ra)
     1154        .set    noreorder
     1155        mfc0    t0,C0_SR
     1156        nop
     1157        and     t0,a0
     1158        mtc0    t0,C0_SR
     1159        j       ra
     1160        nop
     1161ENDFRAME(disable_int)
     1162
     1163
    7351164/*PAGE
    7361165 *
     
    7501179 */
    7511180
     1181#if __mips == 3
     1182
    7521183FRAME(_CPU_Thread_Idle_body,sp,0,ra)
    7531184        wait                    /* enter low power mode */
     
    7561187ENDFRAME(_CPU_Thread_Idle_body)
    7571188
    758 #define VEC_CODE_LENGTH 10*4
     1189#elif __mips == 1
     1190
     1191FRAME(_CPU_Thread_Idle_body,sp,0,ra)
     1192        nop                     /* no wait instruction */
     1193        j _CPU_Thread_Idle_body
     1194        nop
     1195ENDFRAME(_CPU_Thread_Idle_body)
     1196
     1197#else
     1198
     1199   #error "__mips not set to 1 or 3"
     1200   
     1201#endif
    7591202
    7601203/**************************************************************************
     
    7711214***************************************************************************/
    7721215
    773 #define INITEXCFRM ((2*4)+4)            /* ra + 2 arguments */
     1216#define VEC_CODE_LENGTH 10*4
     1217
    7741218FRAME(init_exc_vecs,sp,0,ra)
    775 /* This code yanked from SIM */
    776 #if defined(CPU_R3000)
     1219
     1220#if __mips == 1
     1221
    7771222        .set    noreorder
    7781223        la      t1,exc_utlb_code
     
    7941239        move    t5,ra           # assumes clear_cache doesnt use t5
    7951240        li      a0,UT_VEC
    796         jal     clear_cache
     1241        jal     clear_cache          /* Check out clear cache.... */
    7971242        li      a1,VEC_CODE_LENGTH
    7981243        nop
     
    8041249        nop
    8051250        .set    reorder
    806 #endif
    807 #if defined(CPU_R4000)
     1251
     1252#elif __mips == 3
     1253
    8081254        .set reorder
    8091255        move    t5,ra           # assumes clear_cache doesnt use t5
     
    8751321        move    ra,t5           # restore ra
    8761322        j       ra
    877 #endif
     1323
     1324#else
     1325   #error "__mips not set to 1 or 3"
     1326#endif
     1327
    8781328ENDFRAME(init_exc_vecs)
    879 
    880 
    881 #if defined(CPU_R4000)
    882 FRAME(exc_tlb_code,sp,0,ra)
    883 #ifdef CPU_R3000
    884         la      k0, (R_VEC+((48)*8))
    885 #endif
    886 
    887 #ifdef CPU_R4000
    888         la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    889 #endif
    890         j       k0
    891         nop
    892 
    893 ENDFRAME(exc_tlb_code)
    894 
    895 
    896 FRAME(exc_xtlb_code,sp,0,ra)
    897 #ifdef CPU_R3000
    898         la      k0, (R_VEC+((48)*8))
    899 #endif
    900 
    901 #ifdef CPU_R4000
    902         la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    903 #endif
    904         j       k0
    905         nop
    906 
    907 ENDFRAME(exc_xtlb_code)
    908 
    909 
    910 FRAME(exc_cache_code,sp,0,ra)
    911 #ifdef CPU_R3000
    912         la      k0, (R_VEC+((48)*8))
    913 #endif
    914 
    915 #ifdef CPU_R4000
    916         la      k0, (R_VEC+((112)*8)) /* R4000 Sim's location is different */
    917 #endif
    918         j       k0
    919         nop
    920 
    921 ENDFRAME(exc_cache_code)
    922 
    9231329
    9241330FRAME(exc_norm_code,sp,0,ra)
     
    9261332        j       k0
    9271333        nop
    928         subu    sp, EXCP_STACK_SIZE             /* set up local stack frame */
    9291334ENDFRAME(exc_norm_code)
    930 #endif
    931 
    932 /**************************************************************************
    933 **
    934 ** enable_int(mask) - enables interrupts - mask is positioned so it only
    935 **                      needs to be or'ed into the status reg. This
    936 **                      also does some other things !!!! caution should
    937 **                      be used if invoking this while in the middle
    938 **                      of a debugging session where the client may have
    939 **                      nested interrupts.
    940 **
    941 ****************************************************************************/
    942 FRAME(enable_int,sp,0,ra)
    943         .set    noreorder
    944         mfc0    t0,C0_SR
    945         or      a0,1
    946         or      t0,a0
    947         mtc0    t0,C0_SR
    948         j       ra
    949         nop
    950         .set    reorder
    951 ENDFRAME(enable_int)
    952 
    953 
    954 /***************************************************************************
    955 **
    956 **      disable_int(mask) - disable the interrupt - mask is the complement
    957 **                          of the bits to be cleared - i.e. to clear ext int
    958 **                          5 the mask would be - 0xffff7fff
    959 **
    960 ****************************************************************************/
    961 FRAME(disable_int,sp,0,ra)
    962         .set    noreorder
    963         mfc0    t0,C0_SR
    964         nop
    965         and     t0,a0
    966         mtc0    t0,C0_SR
    967         j       ra
    968         nop
    969 ENDFRAME(disable_int)
    970 
    971 
     1335
     1336/*
     1337** Again, reliance on SIM. Not good.
     1338*/
     1339#if __mips == 3
     1340
     1341FRAME(exc_tlb_code,sp,0,ra)
     1342        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
     1343        j       k0
     1344        nop
     1345ENDFRAME(exc_tlb_code)
     1346
     1347FRAME(exc_xtlb_code,sp,0,ra)
     1348        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
     1349        j       k0
     1350        nop
     1351
     1352ENDFRAME(exc_xtlb_code)
     1353
     1354FRAME(exc_cache_code,sp,0,ra)
     1355        la      k0, (R_VEC+((112)*8)) /* R4000 Sim location */
     1356        j       k0
     1357        nop
     1358ENDFRAME(exc_cache_code)
     1359
     1360#elif __mips == 1
     1361/* ------------------------------------------------------ */
     1362FRAME(exc_tlb_code,sp,0,ra)
     1363        la      k0, (R_VEC+((48)*8))  /* Need something else here besides IDT/SIM call */
     1364        j       k0
     1365        nop
     1366ENDFRAME(exc_tlb_code)
     1367
     1368FRAME(exc_cache_code,sp,0,ra)
     1369        la      k0, (R_VEC+((48)*8))
     1370        j       k0
     1371        nop
     1372ENDFRAME(exc_cache_code)
     1373
     1374#else
     1375
     1376   #error "__mips is not set to 1 or 3"
     1377
     1378#endif
     1379
  • cpukit/score/cpu/mips/idtcpu.h

    r6bb5260 rfda47cd  
    4646#define K2BASE  0xc0000000
    4747#define K2SIZE  0x20000000
    48 #if defined(CPU_R4000)
     48#if  __mips == 3
    4949#define KSBASE  0xe0000000
    5050#define KSSIZE  0x20000000
     
    5757** Exception Vectors
    5858*/
    59 #if defined(CPU_R3000)
     59#if  __mips == 1
    6060#define UT_VEC  K0BASE                  /* utlbmiss vector */
    6161#define E_VEC   (K0BASE+0x80)           /* exception vevtor */
    6262#endif
    63 #if defined(CPU_R4000)
     63#if  __mips == 3
    6464#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
    6565#define X_VEC   (K0BASE+0x080)          /* xtlbmiss vector */
     
    9090#define MAXCACHE        0x40000         /* 256*1024   256k */   
    9191
    92 #if defined(CPU_R4000)
     92#if  __mips == 3
    9393/* R4000 configuration register definitions */
    9494#define CFG_CM          0x80000000      /* Master-Checker mode */
     
    185185** TLB resource defines
    186186*/
    187 #if defined(CPU_R3000)
     187#if  __mips == 1
    188188#define N_TLB_ENTRIES   64
    189189#define TLB_PGSIZE      0x1000
     
    215215#define TLBCTXT_VPNSHIFT        2
    216216#endif
    217 #if defined(CPU_R4000)
     217#if  __mips == 3
    218218#define N_TLB_ENTRIES   48
    219219
     
    250250#endif
    251251
    252 #if defined(CPU_R3000)
     252#if  __mips == 1
    253253#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    254254#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     
    301301#endif
    302302
    303 #if defined(CPU_R4000)
     303#if  __mips == 3
    304304#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    305305#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     
    376376#define C0_INX          $0              /* tlb index */
    377377#define C0_RAND         $1              /* tlb random */
    378 #if defined(CPU_R3000)
     378#if  __mips == 1
    379379#define C0_TLBLO        $2              /* tlb entry low */
    380380#endif
    381 #if defined(CPU_R4000)
     381#if  __mips == 3
    382382#define C0_TLBLO0       $2              /* tlb entry low 0 */
    383383#define C0_TLBLO1       $3              /* tlb entry low 1 */
     
    386386#define C0_CTXT         $4              /* tlb context */
    387387
    388 #if defined(CPU_R4000)
     388#if  __mips == 3
    389389#define C0_PAGEMASK     $5              /* tlb page mask */
    390390#define C0_WIRED        $6              /* number of wired tlb entries */
     
    393393#define C0_BADVADDR     $8              /* bad virtual address */
    394394
    395 #if defined(CPU_R4000)
     395#if  __mips == 3
    396396#define C0_COUNT        $9              /* cycle count */
    397397#endif
     
    399399#define C0_TLBHI        $10             /* tlb entry hi */
    400400
    401 #if defined(CPU_R4000)
     401#if  __mips == 3
    402402#define C0_COMPARE      $11             /* cyccle count comparator  */
    403403#endif
     
    408408#define C0_PRID         $15             /* revision identifier */
    409409
    410 #if defined(CPU_R3000)
     410#if  __mips == 1
    411411#define C0_CONFIG   $3     /* configuration register R3081*/
    412412#endif
    413413
    414 #if defined(CPU_R4000)
     414#if  __mips == 3
    415415#define C0_CONFIG       $16             /* configuration register */
    416416#define C0_LLADDR       $17             /* linked load address */
  • cpukit/score/cpu/mips/iregdef.h

    r6bb5260 rfda47cd  
    222222#define R_CAUSE         68
    223223#define R_TLBHI         69
    224 #if defined(CPU_R3000)
     224#if __mips == 1
    225225#define R_TLBLO         70
    226226#endif
    227 #if defined(CPU_R4000)
     227#if  __mips == 3
    228228#define R_TLBLO0        70
    229229#endif
     
    237237#define R_FCSR          78
    238238#define R_FEIR          79
    239 #if defined(CPU_R3000)
     239#if __mips == 1
    240240#define NREGS           80
    241241#endif
    242 #if defined(CPU_R4000)
     242#if  __mips == 3
    243243#define R_TLBLO1        80
    244244#define R_PAGEMASK      81
     
    297297
    298298/* Ketan added the following */
    299 #ifdef CPU_R3000
     299#ifdef __mips == 1
    300300#define sreg    sw
    301301#define lreg    lw
     
    303303#define rmtc0   mtc0
    304304#define R_SZ    4
    305 #endif CPU_R3000
    306 
    307 #ifdef CPU_R4000
     305#endif /* __mips == 1 */
     306
     307/* #ifdef  __mips == 3 */
    308308#if __mips < 3
    309309#define sreg    sw
     
    319319#define R_SZ    8
    320320#endif
    321 #endif CPU_R4000
     321/* #endif __mips == 3 */
    322322/* Ketan till here */
    323323
  • cpukit/score/cpu/mips/rtems/asm.h

    r6bb5260 rfda47cd  
    2525/* @(#)asm.h       03/15/96     1.1 */
    2626
    27 #ifndef __MIPS64ORION_ASM_h
    28 #define __MIPS64ORION_ASM_h
     27#ifndef __NO_CPU_ASM_h
     28#define __NO_CPU_ASM_h
    2929
    3030/*
     
    9797#define EXTERN(sym) .globl SYM (sym)
    9898
     99/*
     100 *  Debugger macros for assembly language routines. Allows the
     101 *  programmer to set up the necessary stack frame info
     102 *  required by debuggers to do stack traces.
     103 */
     104
     105#ifndef XDS
     106#define FRAME(name,frm_reg,offset,ret_reg)      \
     107        .globl  name;                           \
     108        .ent    name;                           \
     109name:;                                          \
     110        .frame  frm_reg,offset,ret_reg
     111#define ENDFRAME(name)                          \
     112        .end name
     113#else
     114#define FRAME(name,frm_reg,offset,ret_reg)      \
     115        .globl  _##name;\
     116_##name:
     117#define ENDFRAME(name)
     118#endif  XDS
     119
    99120#endif
    100121/* end of include file */
    101122
    102 
  • cpukit/score/cpu/mips/rtems/mips/idtcpu.h

    r6bb5260 rfda47cd  
    4646#define K2BASE  0xc0000000
    4747#define K2SIZE  0x20000000
    48 #if defined(CPU_R4000)
     48#if  __mips == 3
    4949#define KSBASE  0xe0000000
    5050#define KSSIZE  0x20000000
     
    5757** Exception Vectors
    5858*/
    59 #if defined(CPU_R3000)
     59#if  __mips == 1
    6060#define UT_VEC  K0BASE                  /* utlbmiss vector */
    6161#define E_VEC   (K0BASE+0x80)           /* exception vevtor */
    6262#endif
    63 #if defined(CPU_R4000)
     63#if  __mips == 3
    6464#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
    6565#define X_VEC   (K0BASE+0x080)          /* xtlbmiss vector */
     
    9090#define MAXCACHE        0x40000         /* 256*1024   256k */   
    9191
    92 #if defined(CPU_R4000)
     92#if  __mips == 3
    9393/* R4000 configuration register definitions */
    9494#define CFG_CM          0x80000000      /* Master-Checker mode */
     
    185185** TLB resource defines
    186186*/
    187 #if defined(CPU_R3000)
     187#if  __mips == 1
    188188#define N_TLB_ENTRIES   64
    189189#define TLB_PGSIZE      0x1000
     
    215215#define TLBCTXT_VPNSHIFT        2
    216216#endif
    217 #if defined(CPU_R4000)
     217#if  __mips == 3
    218218#define N_TLB_ENTRIES   48
    219219
     
    250250#endif
    251251
    252 #if defined(CPU_R3000)
     252#if  __mips == 1
    253253#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    254254#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     
    301301#endif
    302302
    303 #if defined(CPU_R4000)
     303#if  __mips == 3
    304304#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    305305#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     
    376376#define C0_INX          $0              /* tlb index */
    377377#define C0_RAND         $1              /* tlb random */
    378 #if defined(CPU_R3000)
     378#if  __mips == 1
    379379#define C0_TLBLO        $2              /* tlb entry low */
    380380#endif
    381 #if defined(CPU_R4000)
     381#if  __mips == 3
    382382#define C0_TLBLO0       $2              /* tlb entry low 0 */
    383383#define C0_TLBLO1       $3              /* tlb entry low 1 */
     
    386386#define C0_CTXT         $4              /* tlb context */
    387387
    388 #if defined(CPU_R4000)
     388#if  __mips == 3
    389389#define C0_PAGEMASK     $5              /* tlb page mask */
    390390#define C0_WIRED        $6              /* number of wired tlb entries */
     
    393393#define C0_BADVADDR     $8              /* bad virtual address */
    394394
    395 #if defined(CPU_R4000)
     395#if  __mips == 3
    396396#define C0_COUNT        $9              /* cycle count */
    397397#endif
     
    399399#define C0_TLBHI        $10             /* tlb entry hi */
    400400
    401 #if defined(CPU_R4000)
     401#if  __mips == 3
    402402#define C0_COMPARE      $11             /* cyccle count comparator  */
    403403#endif
     
    408408#define C0_PRID         $15             /* revision identifier */
    409409
    410 #if defined(CPU_R3000)
     410#if  __mips == 1
    411411#define C0_CONFIG   $3     /* configuration register R3081*/
    412412#endif
    413413
    414 #if defined(CPU_R4000)
     414#if  __mips == 3
    415415#define C0_CONFIG       $16             /* configuration register */
    416416#define C0_LLADDR       $17             /* linked load address */
  • cpukit/score/cpu/mips/rtems/mips/iregdef.h

    r6bb5260 rfda47cd  
    222222#define R_CAUSE         68
    223223#define R_TLBHI         69
    224 #if defined(CPU_R3000)
     224#if __mips == 1
    225225#define R_TLBLO         70
    226226#endif
    227 #if defined(CPU_R4000)
     227#if  __mips == 3
    228228#define R_TLBLO0        70
    229229#endif
     
    237237#define R_FCSR          78
    238238#define R_FEIR          79
    239 #if defined(CPU_R3000)
     239#if __mips == 1
    240240#define NREGS           80
    241241#endif
    242 #if defined(CPU_R4000)
     242#if  __mips == 3
    243243#define R_TLBLO1        80
    244244#define R_PAGEMASK      81
     
    297297
    298298/* Ketan added the following */
    299 #ifdef CPU_R3000
     299#ifdef __mips == 1
    300300#define sreg    sw
    301301#define lreg    lw
     
    303303#define rmtc0   mtc0
    304304#define R_SZ    4
    305 #endif CPU_R3000
    306 
    307 #ifdef CPU_R4000
     305#endif /* __mips == 1 */
     306
     307/* #ifdef  __mips == 3 */
    308308#if __mips < 3
    309309#define sreg    sw
     
    319319#define R_SZ    8
    320320#endif
    321 #endif CPU_R4000
     321/* #endif __mips == 3 */
    322322/* Ketan till here */
    323323
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r6bb5260 rfda47cd  
    1919 *      of this software for any purpose.
    2020 *
    21  *  Derived from source copyrighted as follows:
     21 *  Derived from c/src/exec/score/cpu/no_cpu/cpu.h:
    2222 *
    2323 *  COPYRIGHT (c) 1989-1999.
     
    9494 *  Does RTEMS manage a dedicated interrupt stack in software?
    9595 *
    96  *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
     96 *  If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
    9797 *  If FALSE, nothing is done.
    9898 *
     
    163163 *  the answer is TRUE.
    164164 *
    165  *  The macro name "MIPS64ORION_HAS_FPU" should be made CPU specific.
     165 *  The macro name "MIPS_HAS_FPU" should be made CPU specific.
    166166 *  It indicates whether or not this CPU model has FP support.  For
    167167 *  example, it would be possible to have an i386_nofp CPU model
     
    170170 */
    171171
    172 #if ( MIPS64ORION_HAS_FPU == 1 )
     172#if ( MIPS_HAS_FPU == 1 )
    173173#define CPU_HARDWARE_FP     TRUE
    174174#else
    175175#define CPU_HARDWARE_FP     FALSE
    176176#endif
    177 #define CPU_SOFTWARE_FP     FALSE
    178177
    179178/*
     
    445444
    446445/*
    447  *  Macros to access MIPS64ORION specific additions to the CPU Table
     446 *  Macros to access MIPS specific additions to the CPU Table
    448447 */
    449448
  • cpukit/score/cpu/mips/rtems/score/mips.h

    r6bb5260 rfda47cd  
    1616 *      of this software for any purpose.
    1717 *
    18  *  Derived from source copyrighted as follows:
     18 *  Derived from c/src/exec/score/cpu/no_cpu/no_cpu.h:
    1919 *
    2020 *  COPYRIGHT (c) 1989-1999.
     
    2929/* @(#)mips64orion.h       08/29/96     1.3 */
    3030
    31 #ifndef _INCLUDE_MIPS64ORION_h
    32 #define _INCLUDE_MIPS64ORION_h
     31#ifndef _INCLUDE_MIPS_h
     32#define _INCLUDE_MIPS_h
    3333
    3434#ifdef __cplusplus
     
    4545 */
    4646 
    47 #if defined(rtems_multilib)
    48 /*
    49  *  Figure out all CPU Model Feature Flags based upon compiler
    50  *  predefines.
    51  */
     47#if defined(__mips_soft_float)
     48#define MIPS_HAS_FPU 0
     49#else
     50#define MIPS_HAS_FPU 1
     51#endif
    5252
    53 #define CPU_MODEL_NAME  "rtems_multilib"
    54 #define MIPS64ORION_HAS_FPU     1
    55 
    56 #elif defined(R4650)
    57  
    58 #define CPU_MODEL_NAME  "R4650"
    59 #define MIPS64ORION_HAS_FPU     1
    60  
    61 #elif defined(R4600)
    62  
    63 #define CPU_MODEL_NAME  "R4600"
    64 #define MIPS64ORION_HAS_FPU     1
    65 
     53#if (__mips == 1)
     54#define CPU_MODEL_NAME  "ISA Level 1 or 2"
     55#elif (__mips == 3)
     56#if defined(__mips64)
     57#define CPU_MODEL_NAME  "ISA Level 4"
    6658#else
    67  
    68 #error "Unsupported CPU Model"
    69  
     59#define CPU_MODEL_NAME  "ISA Level 3"
     60#endif
     61#else
     62#error "Unknown MIPS ISA level"
    7063#endif
    7164
     
    7467 */
    7568
    76 #define CPU_NAME "MIPS R46xxx"
     69#define CPU_NAME "MIPS"
    7770
    7871#ifdef __cplusplus
     
    8073#endif
    8174
    82 #endif /* ! _INCLUDE_MIPS64ORION_h */
     75#endif /* ! _INCLUDE_MIPS_h */
    8376/* end of include file */
Note: See TracChangeset for help on using the changeset viewer.