Index: c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
===================================================================
--- c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h	(revision a114f99bd28cd534b1446d2d85ea681ef1832955)
+++ c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h	(revision fd6cd36b09607cd79d87fddc902500f888f3f8b2)
@@ -25,4 +25,5 @@
 
 #include <libcpu/arm-cp15.h>
+#include "../include/arm-cache-l1.h"
 
 #define CPU_DATA_CACHE_ALIGNMENT 32
@@ -33,12 +34,42 @@
 #endif
 
+#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
+          ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
+
+
 static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
 {
-  arm_cp15_data_cache_clean_line(d_addr);
+  arm_cache_l1_flush_1_data_line(d_addr);
+}
+
+static inline void
+_CPU_cache_flush_data_range(
+  const void *d_addr,
+  size_t      n_bytes
+)
+{
+  _ARM_Data_synchronization_barrier();
+  arm_cp15_drain_write_buffer();
+  arm_cache_l1_flush_data_range(
+    d_addr,
+    n_bytes
+  );
 }
 
 static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
 {
-  arm_cp15_data_cache_invalidate_line(d_addr);
+  arm_cache_l1_invalidate_1_data_line(d_addr);
+}
+
+static inline void
+_CPU_cache_invalidate_data_range(
+  const void *addr_first,
+  size_t     n_bytes
+)
+{
+  arm_cache_l1_invalidate_data_range(
+    addr_first,
+    n_bytes
+  );
 }
 
@@ -55,5 +86,11 @@
 static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
 {
-  arm_cp15_instruction_cache_invalidate_line(d_addr);
+  arm_cache_l1_invalidate_1_instruction_line(d_addr);
+}
+
+static inline void
+_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
+{
+  arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
 }
 
Index: c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
===================================================================
--- c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h	(revision a114f99bd28cd534b1446d2d85ea681ef1832955)
+++ c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h	(revision fd6cd36b09607cd79d87fddc902500f888f3f8b2)
@@ -38,6 +38,8 @@
 #define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
 
-#define ARM_CACHE_L1_CSS_ID_DATA 0
-#define ARM_CACHE_L1_CSS_ID_INSTRUCTION 1
+#define ARM_CACHE_L1_CSS_ID_DATA \
+          (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
+#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
+          (ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
 #define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
 #define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
@@ -51,13 +53,4 @@
   _ARM_Data_synchronization_barrier();
 #endif
-}
-
-static void arm_cache_l1_select( const uint32_t selection )
-{
-  /* select current cache level in cssr */
-  arm_cp15_set_cache_size_selection( selection );
-
-  /* isb to sych the new cssr&csidr */
-  _ARM_Instruction_synchronization_barrier();
 }
 
@@ -70,20 +63,21 @@
  * */
 
-static inline void arm_cache_l1_properties( 
+static inline void arm_cache_l1_properties_for_level(
   uint32_t *l1LineSize,
   uint32_t *l1Associativity,
-  uint32_t *l1NumSets )
-{
-  uint32_t id;
-
-  _ARM_Instruction_synchronization_barrier();
-  id               = arm_cp15_get_cache_size_id();
+  uint32_t *l1NumSets,
+  uint32_t level_and_inst_dat
+)
+{
+  uint32_t ccsidr;
+
+  ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
 
   /* Cache line size in words + 2 -> bytes) */
-  *l1LineSize      = ( id & 0x0007U ) + 2 + 2;
+  *l1LineSize      = arm_ccsidr_get_line_power(ccsidr);
   /* Number of Ways */
-  *l1Associativity = ( ( id >> 3 ) & 0x03ffU ) + 1; 
+  *l1Associativity = arm_ccsidr_get_associativity(ccsidr);
   /* Number of Sets */
-  *l1NumSets       = ( ( id >> 13 ) & 0x7fffU ) + 1;
+  *l1NumSets       = arm_ccsidr_get_num_sets(ccsidr);
 }
 
@@ -131,6 +125,7 @@
 
   /* Get the L1 cache properties */
-  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
-                                     &l1NumSets );
+  arm_cache_l1_properties_for_level( &l1LineSize,
+                    &l1Associativity, &l1NumSets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   for ( w = 0; w < l1Associativity; ++w ) {
@@ -161,6 +156,7 @@
 
   /* Get the L1 cache properties */
-  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
-                                     &l1NumSets );
+  arm_cache_l1_properties_for_level( &l1LineSize,
+                    &l1Associativity, &l1NumSets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   for ( w = 0; w < l1Associativity; ++w ) {
@@ -192,6 +188,7 @@
 
   /* Get the L1 cache properties */
-  arm_cache_l1_properties( &l1LineSize, &l1Associativity,
-                                     &l1NumSets );
+  arm_cache_l1_properties_for_level( &l1LineSize,
+                    &l1Associativity, &l1NumSets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   for ( w = 0; w < l1Associativity; ++w ) {
@@ -372,5 +369,4 @@
 static inline size_t arm_cache_l1_get_data_cache_size( void )
 {
-  rtems_interrupt_level level;
   size_t   size;
   uint32_t line_size     = 0;
@@ -378,11 +374,7 @@
   uint32_t num_sets      = 0;
 
-  rtems_interrupt_local_disable(level);
-
-  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
-  arm_cache_l1_properties( &line_size, &associativity,
-                           &num_sets );
-
-  rtems_interrupt_local_enable(level);
+  arm_cache_l1_properties_for_level( &line_size,
+                    &associativity, &num_sets,
+                    ARM_CACHE_L1_CSS_ID_DATA);
 
   size = (1 << line_size) * associativity * num_sets;
@@ -393,5 +385,4 @@
 static inline size_t arm_cache_l1_get_instruction_cache_size( void )
 {
-  rtems_interrupt_level level;
   size_t   size;
   uint32_t line_size     = 0;
@@ -399,14 +390,10 @@
   uint32_t num_sets      = 0;
 
-  rtems_interrupt_local_disable(level);
-
-  arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
-  arm_cache_l1_properties( &line_size, &associativity,
-                           &num_sets );
-
-  rtems_interrupt_local_enable(level);
+  arm_cache_l1_properties_for_level( &line_size,
+                    &associativity, &num_sets,
+                    ARM_CACHE_L1_CSS_ID_INSTRUCTION);
 
   size = (1 << line_size) * associativity * num_sets;
-  
+
   return size;
 }
Index: c/src/lib/libcpu/arm/shared/include/arm-cp15.h
===================================================================
--- c/src/lib/libcpu/arm/shared/include/arm-cp15.h	(revision a114f99bd28cd534b1446d2d85ea681ef1832955)
+++ c/src/lib/libcpu/arm/shared/include/arm-cp15.h	(revision fd6cd36b09607cd79d87fddc902500f888f3f8b2)
@@ -211,4 +211,16 @@
 /** @} */
 
+/**
+ * @name CCSIDR, Cache Size ID Register Defines
+ *
+ * @{
+ */
+
+#define ARM_CP15_CACHE_CSS_ID_DATA 0
+#define ARM_CP15_CACHE_CSS_ID_INSTRUCTION 1
+#define ARM_CP15_CACHE_CSS_LEVEL(level) ((level) << 1)
+
+/** @} */
+
 ARM_CP15_TEXT_SECTION static inline uint32_t
 arm_cp15_get_id_code(void)
@@ -820,4 +832,19 @@
 }
 
+ARM_CP15_TEXT_SECTION static inline uint32_t
+arm_cp15_get_cache_size_id_for_level(uint32_t level_and_inst_dat)
+{
+  rtems_interrupt_level irq_level;
+  uint32_t ccsidr;
+
+  rtems_interrupt_local_disable(irq_level);
+  arm_cp15_set_cache_size_selection(level_and_inst_dat);
+  _ARM_Instruction_synchronization_barrier();
+  ccsidr = arm_cp15_get_cache_size_id();
+  rtems_interrupt_local_enable(irq_level);
+
+  return ccsidr;
+}
+
 ARM_CP15_TEXT_SECTION static inline void
 arm_cp15_cache_invalidate(void)
@@ -1037,8 +1064,6 @@
       uint32_t way_shift;
 
-      arm_cp15_set_cache_size_selection(level << 1);
-      _ARM_Instruction_synchronization_barrier();
-
-      ccsidr = arm_cp15_get_cache_size_id();
+      ccsidr = arm_cp15_get_cache_size_id_for_level(level << 1);
+
       line_power = arm_ccsidr_get_line_power(ccsidr);
       associativity = arm_ccsidr_get_associativity(ccsidr);
