Changeset fd6cd36 in rtems


Ignore:
Timestamp:
Jul 3, 2016, 11:30:05 PM (3 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
4.11
Children:
0d77c4f2
Parents:
a114f99b
git-author:
Pavel Pisa <pisa@…> (07/03/16 23:30:05)
git-committer:
Pavel Pisa <pisa@…> (10/02/16 08:40:33)
Message:

bsps/arm: basic on core cache support changed to use l1 functions.

The basic data and instruction rage functions should be compatible
for all ARMv4,5,6,7 functions. On the other hand, some functions
are not portable, for example arm_cp15_data_cache_test_and_clean()
and arm_cp15_data_cache_invalidate() for all versions and there
has to be specialized version for newer cores.
arm_cache_l1_properties_for_level uses CCSIDR which is not present
on older chips.

Actual version is only experimental, needs more changes
and problem has been found on RPi1 with dlopen so there seems
to be real problem.

Updates #2783
Updates #2782

Location:
c/src/lib
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h

    ra114f99b rfd6cd36  
    2525
    2626#include <libcpu/arm-cp15.h>
     27#include "../include/arm-cache-l1.h"
    2728
    2829#define CPU_DATA_CACHE_ALIGNMENT 32
     
    3334#endif
    3435
     36#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
     37          ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
     38
     39
    3540static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
    3641{
    37   arm_cp15_data_cache_clean_line(d_addr);
     42  arm_cache_l1_flush_1_data_line(d_addr);
     43}
     44
     45static inline void
     46_CPU_cache_flush_data_range(
     47  const void *d_addr,
     48  size_t      n_bytes
     49)
     50{
     51  _ARM_Data_synchronization_barrier();
     52  arm_cp15_drain_write_buffer();
     53  arm_cache_l1_flush_data_range(
     54    d_addr,
     55    n_bytes
     56  );
    3857}
    3958
    4059static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
    4160{
    42   arm_cp15_data_cache_invalidate_line(d_addr);
     61  arm_cache_l1_invalidate_1_data_line(d_addr);
     62}
     63
     64static inline void
     65_CPU_cache_invalidate_data_range(
     66  const void *addr_first,
     67  size_t     n_bytes
     68)
     69{
     70  arm_cache_l1_invalidate_data_range(
     71    addr_first,
     72    n_bytes
     73  );
    4374}
    4475
     
    5586static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
    5687{
    57   arm_cp15_instruction_cache_invalidate_line(d_addr);
     88  arm_cache_l1_invalidate_1_instruction_line(d_addr);
     89}
     90
     91static inline void
     92_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
     93{
     94  arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
    5895}
    5996
  • c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h

    ra114f99b rfd6cd36  
    3838#define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
    3939
    40 #define ARM_CACHE_L1_CSS_ID_DATA 0
    41 #define ARM_CACHE_L1_CSS_ID_INSTRUCTION 1
     40#define ARM_CACHE_L1_CSS_ID_DATA \
     41          (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0))
     42#define ARM_CACHE_L1_CSS_ID_INSTRUCTION \
     43          (ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0))
    4244#define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 )
    4345#define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \
     
    5153  _ARM_Data_synchronization_barrier();
    5254#endif
    53 }
    54 
    55 static void arm_cache_l1_select( const uint32_t selection )
    56 {
    57   /* select current cache level in cssr */
    58   arm_cp15_set_cache_size_selection( selection );
    59 
    60   /* isb to sych the new cssr&csidr */
    61   _ARM_Instruction_synchronization_barrier();
    6255}
    6356
     
    7063 * */
    7164
    72 static inline void arm_cache_l1_properties(
     65static inline void arm_cache_l1_properties_for_level(
    7366  uint32_t *l1LineSize,
    7467  uint32_t *l1Associativity,
    75   uint32_t *l1NumSets )
    76 {
    77   uint32_t id;
    78 
    79   _ARM_Instruction_synchronization_barrier();
    80   id               = arm_cp15_get_cache_size_id();
     68  uint32_t *l1NumSets,
     69  uint32_t level_and_inst_dat
     70)
     71{
     72  uint32_t ccsidr;
     73
     74  ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat);
    8175
    8276  /* Cache line size in words + 2 -> bytes) */
    83   *l1LineSize      = ( id & 0x0007U ) + 2 + 2;
     77  *l1LineSize      = arm_ccsidr_get_line_power(ccsidr);
    8478  /* Number of Ways */
    85   *l1Associativity = ( ( id >> 3 ) & 0x03ffU ) + 1;
     79  *l1Associativity = arm_ccsidr_get_associativity(ccsidr);
    8680  /* Number of Sets */
    87   *l1NumSets       = ( ( id >> 13 ) & 0x7fffU ) + 1;
     81  *l1NumSets       = arm_ccsidr_get_num_sets(ccsidr);
    8882}
    8983
     
    131125
    132126  /* Get the L1 cache properties */
    133   arm_cache_l1_properties( &l1LineSize, &l1Associativity,
    134                                      &l1NumSets );
     127  arm_cache_l1_properties_for_level( &l1LineSize,
     128                    &l1Associativity, &l1NumSets,
     129                    ARM_CACHE_L1_CSS_ID_DATA);
    135130
    136131  for ( w = 0; w < l1Associativity; ++w ) {
     
    161156
    162157  /* Get the L1 cache properties */
    163   arm_cache_l1_properties( &l1LineSize, &l1Associativity,
    164                                      &l1NumSets );
     158  arm_cache_l1_properties_for_level( &l1LineSize,
     159                    &l1Associativity, &l1NumSets,
     160                    ARM_CACHE_L1_CSS_ID_DATA);
    165161
    166162  for ( w = 0; w < l1Associativity; ++w ) {
     
    192188
    193189  /* Get the L1 cache properties */
    194   arm_cache_l1_properties( &l1LineSize, &l1Associativity,
    195                                      &l1NumSets );
     190  arm_cache_l1_properties_for_level( &l1LineSize,
     191                    &l1Associativity, &l1NumSets,
     192                    ARM_CACHE_L1_CSS_ID_DATA);
    196193
    197194  for ( w = 0; w < l1Associativity; ++w ) {
     
    372369static inline size_t arm_cache_l1_get_data_cache_size( void )
    373370{
    374   rtems_interrupt_level level;
    375371  size_t   size;
    376372  uint32_t line_size     = 0;
     
    378374  uint32_t num_sets      = 0;
    379375
    380   rtems_interrupt_local_disable(level);
    381 
    382   arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA );
    383   arm_cache_l1_properties( &line_size, &associativity,
    384                            &num_sets );
    385 
    386   rtems_interrupt_local_enable(level);
     376  arm_cache_l1_properties_for_level( &line_size,
     377                    &associativity, &num_sets,
     378                    ARM_CACHE_L1_CSS_ID_DATA);
    387379
    388380  size = (1 << line_size) * associativity * num_sets;
     
    393385static inline size_t arm_cache_l1_get_instruction_cache_size( void )
    394386{
    395   rtems_interrupt_level level;
    396387  size_t   size;
    397388  uint32_t line_size     = 0;
     
    399390  uint32_t num_sets      = 0;
    400391
    401   rtems_interrupt_local_disable(level);
    402 
    403   arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
    404   arm_cache_l1_properties( &line_size, &associativity,
    405                            &num_sets );
    406 
    407   rtems_interrupt_local_enable(level);
     392  arm_cache_l1_properties_for_level( &line_size,
     393                    &associativity, &num_sets,
     394                    ARM_CACHE_L1_CSS_ID_INSTRUCTION);
    408395
    409396  size = (1 << line_size) * associativity * num_sets;
    410  
     397
    411398  return size;
    412399}
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    ra114f99b rfd6cd36  
    211211/** @} */
    212212
     213/**
     214 * @name CCSIDR, Cache Size ID Register Defines
     215 *
     216 * @{
     217 */
     218
     219#define ARM_CP15_CACHE_CSS_ID_DATA 0
     220#define ARM_CP15_CACHE_CSS_ID_INSTRUCTION 1
     221#define ARM_CP15_CACHE_CSS_LEVEL(level) ((level) << 1)
     222
     223/** @} */
     224
    213225ARM_CP15_TEXT_SECTION static inline uint32_t
    214226arm_cp15_get_id_code(void)
     
    820832}
    821833
     834ARM_CP15_TEXT_SECTION static inline uint32_t
     835arm_cp15_get_cache_size_id_for_level(uint32_t level_and_inst_dat)
     836{
     837  rtems_interrupt_level irq_level;
     838  uint32_t ccsidr;
     839
     840  rtems_interrupt_local_disable(irq_level);
     841  arm_cp15_set_cache_size_selection(level_and_inst_dat);
     842  _ARM_Instruction_synchronization_barrier();
     843  ccsidr = arm_cp15_get_cache_size_id();
     844  rtems_interrupt_local_enable(irq_level);
     845
     846  return ccsidr;
     847}
     848
    822849ARM_CP15_TEXT_SECTION static inline void
    823850arm_cp15_cache_invalidate(void)
     
    10371064      uint32_t way_shift;
    10381065
    1039       arm_cp15_set_cache_size_selection(level << 1);
    1040       _ARM_Instruction_synchronization_barrier();
    1041 
    1042       ccsidr = arm_cp15_get_cache_size_id();
     1066      ccsidr = arm_cp15_get_cache_size_id_for_level(level << 1);
     1067
    10431068      line_power = arm_ccsidr_get_line_power(ccsidr);
    10441069      associativity = arm_ccsidr_get_associativity(ccsidr);
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