Changeset fd51f7e in rtems for c/src/lib/libcpu/arm


Ignore:
Timestamp:
May 2, 2013, 9:09:24 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
ecf7dd9
Parents:
88cf23f
git-author:
Sebastian Huber <sebastian.huber@…> (05/02/13 09:09:24)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/03/13 15:30:55)
Message:

bsps/arm: Support ARMv7 VMSA sections and control

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    r88cf23f rfd51f7e  
    5454#define ARM_MMU_SECT_BASE_SHIFT 20
    5555#define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT)
    56 #define ARM_MMU_SECT_DOMAIN_SHIFT 5
    57 #define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT)
     56#define ARM_MMU_SECT_NS (1U << 19)
     57#define ARM_MMU_SECT_NG (1U << 17)
     58#define ARM_MMU_SECT_S (1U << 16)
     59#define ARM_MMU_SECT_AP_2 (1U << 15)
     60#define ARM_MMU_SECT_TEX_2 (1U << 14)
     61#define ARM_MMU_SECT_TEX_1 (1U << 13)
     62#define ARM_MMU_SECT_TEX_0 (1U << 12)
     63#define ARM_MMU_SECT_TEX_SHIFT 12
     64#define ARM_MMU_SECT_TEX_MASK (0x3U << ARM_MMU_SECT_TEX_SHIFT)
    5865#define ARM_MMU_SECT_AP_1 (1U << 11)
    5966#define ARM_MMU_SECT_AP_0 (1U << 10)
    6067#define ARM_MMU_SECT_AP_SHIFT 10
    61 #define ARM_MMU_SECT_AP_MASK (0x3U << ARM_MMU_SECT_AP_SHIFT)
     68#define ARM_MMU_SECT_AP_MASK (0x23U << ARM_MMU_SECT_AP_SHIFT)
     69#define ARM_MMU_SECT_DOMAIN_SHIFT 5
     70#define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT)
     71#define ARM_MMU_SECT_XN (1U << 4)
    6272#define ARM_MMU_SECT_C (1U << 3)
    6373#define ARM_MMU_SECT_B (1U << 2)
    64 #define ARM_MMU_SECT_DEFAULT 0x12U
     74#define ARM_MMU_SECT_PXN (1U << 0)
     75#define ARM_MMU_SECT_DEFAULT 0x2U
    6576#define ARM_MMU_SECT_GET_INDEX(mva) \
    6677  (((uint32_t) (mva)) >> ARM_MMU_SECT_BASE_SHIFT)
     
    8091 */
    8192
     93#define ARM_CP15_CTRL_TE (1U << 30)
     94#define ARM_CP15_CTRL_AFE (1U << 29)
     95#define ARM_CP15_CTRL_TRE (1U << 28)
     96#define ARM_CP15_CTRL_NMFI (1U << 27)
     97#define ARM_CP15_CTRL_EE (1U << 25)
     98#define ARM_CP15_CTRL_VE (1U << 24)
     99#define ARM_CP15_CTRL_U (1U << 22)
     100#define ARM_CP15_CTRL_FI (1U << 21)
     101#define ARM_CP15_CTRL_UWXN (1U << 20)
     102#define ARM_CP15_CTRL_WXN (1U << 19)
     103#define ARM_CP15_CTRL_HA (1U << 17)
    82104#define ARM_CP15_CTRL_L4 (1U << 15)
    83105#define ARM_CP15_CTRL_RR (1U << 14)
    84106#define ARM_CP15_CTRL_V (1U << 13)
    85107#define ARM_CP15_CTRL_I (1U << 12)
     108#define ARM_CP15_CTRL_Z (1U << 11)
     109#define ARM_CP15_CTRL_SW (1U << 10)
    86110#define ARM_CP15_CTRL_R (1U << 9)
    87111#define ARM_CP15_CTRL_S (1U << 8)
    88112#define ARM_CP15_CTRL_B (1U << 7)
     113#define ARM_CP15_CTRL_CP15BEN (1U << 5)
    89114#define ARM_CP15_CTRL_C (1U << 2)
    90115#define ARM_CP15_CTRL_A (1U << 1)
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